From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-0.8 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 90EF2C54FC9 for ; Tue, 21 Apr 2020 17:39:50 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7F00720724 for ; Tue, 21 Apr 2020 17:39:50 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729249AbgDURjq (ORCPT ); Tue, 21 Apr 2020 13:39:46 -0400 Received: from muru.com ([72.249.23.125]:50688 "EHLO muru.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1729234AbgDURjq (ORCPT ); Tue, 21 Apr 2020 13:39:46 -0400 Received: from atomide.com (localhost [127.0.0.1]) by muru.com (Postfix) with ESMTPS id C057C8081; Tue, 21 Apr 2020 17:40:29 +0000 (UTC) Date: Tue, 21 Apr 2020 10:39:38 -0700 From: Tony Lindgren To: "H. Nikolaus Schaller" Cc: Maxime Ripard , Philipp Rossak , Jonathan Bakker , David Airlie , Daniel Vetter , Rob Herring , Mark Rutland , =?utf-8?Q?Beno=C3=AEt?= Cousson , Paul Cercueil , Ralf Baechle , Paul Burton , James Hogan , Kukjin Kim , Krzysztof Kozlowski , Chen-Yu Tsai , Thomas Bogendoerfer , "open list:DRM PANEL DRIVERS" , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , Linux Kernel Mailing List , linux-omap , OpenPVRSGX Linux Driver Group , Discussions about the Letux Kernel , kernel@pyra-handheld.com, linux-mips@vger.kernel.org, arm-soc , linux-samsung-soc@vger.kernel.org Subject: Re: [PATCH v6 00/12] ARM/MIPS: DTS: add child nodes describing the PVRSGX GPU present in some OMAP SoC and JZ4780 (and many more) Message-ID: <20200421173938.GZ37466@atomide.com> References: <20200415101008.zxzxca2vlfsefpdv@gilmour.lan> <2E3401F1-A106-4396-8FE6-51CAB72926A4@goldelico.com> <20200415130233.rgn7xrtwqicptke2@gilmour.lan> <10969e64-fe1f-d692-4984-4ba916bd2161@gmail.com> <20200420073842.nx4xb3zqvu23arkc@gilmour.lan> <20200421112129.zjmkmzo3aftksgka@gilmour.lan> <20200421141543.GU37466@atomide.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-mips-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org * H. Nikolaus Schaller [200421 17:31]: > > Am 21.04.2020 um 16:15 schrieb Tony Lindgren : > > Note that on omaps there are actually SoC module specific registers. > > Ah, I see. This is of course a difference that the TI glue logic has > its own registers in the same address range as the sgx and this can't > be easily handled by a common sgx driver. > > This indeed seems to be unique with omap. > > > And there can be multiple devices within a single target module on > > omaps. So the extra dts node and device is justified there. > > > > For other SoCs, the SGX clocks are probably best handled directly > > in pvr-drv.c PM runtime functions unless a custom hardware wrapper > > with SoC specific registers exists. > > That is why we need to evaluate what the better strategy is. > > So we have > a) omap which has a custom wrapper around the sgx > b) others without, i.e. an empty (or pass-through) wrapper > > Which one do we make the "standard" and which one the "exception"? > What are good reasons for either one? The wrapper is already handled by the ti-sysc binding, the sgx binding should be standard with optional clocks. See for example the standard 8250 uart for am335x with: $ git grep -B20 -A10 uart0 arch/arm/boot/dts/am33xx-l4.dtsi The 8250 device configuration is described in the standard 8250 dts binding, and the am335x module in the ti-sysc binding. The are separate devices :) So for the sgx binding, you can just leave out TI specific module wrapper completely from the example. > It also allows to handle different number of clocks (A31 seems to > need 4, Samsung, A83 and JZ4780 one) without changing the sgx bindings > or making big lists of conditionals. This variance would be handled > outside the sgx core bindings and driver. Well if other SoCs implement genpd domains etc, that's then again part of a separate binding and not part of the sgx binding. Regards, Tony