From: Boris Brezillon <boris.brezillon@collabora.com>
To: "Ramuthevar,
Vadivel MuruganX" <vadivel.muruganx.ramuthevar@linux.intel.com>
Cc: qi-ming.wu@intel.com, linux-kernel@vger.kernel.org,
linux-mtd@lists.infradead.org, devicetree@vger.kernel.org,
cheol.yong.kim@intel.com, hauke.mehrtens@intel.com,
anders.roxell@linaro.org, vigneshr@ti.com, arnd@arndb.de,
richard@nod.at, brendanhiggins@google.com,
linux-mips@vger.kernel.org, robh+dt@kernel.org,
miquel.raynal@bootlin.com, tglx@linutronix.de,
masonccyang@mxic.com.tw, andriy.shevchenko@intel.com
Subject: Re: [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC
Date: Thu, 30 Apr 2020 10:36:58 +0200 [thread overview]
Message-ID: <20200430103658.4b0b979e@collabora.com> (raw)
In-Reply-To: <1df71cf7-4cae-4cd0-864c-0812bb2cc123@linux.intel.com>
On Thu, 30 Apr 2020 16:30:15 +0800
"Ramuthevar, Vadivel MuruganX"
<vadivel.muruganx.ramuthevar@linux.intel.com> wrote:
> >>>
> >>> And now I'd like you to explain why 5 is the right value for that field
> >>> (I guess that has to do with the position of the CS/ALE/CLE pins).
> >>
> >> 5 : bit 26, 25, 24, 23, 22 to be included for comparison in the
> >
> > That's 6 bits to me, not 5.
>
> No , 5 bits only the above case.
Oops, right, sorry for the brain fart.
> >
> > The question is, is it the same value we have in nand_pa or it is
> > different?
> >
> Different address which is 0xE1400000 NAND_BASE_PHY address.
Then why didn't you tell me they didn't match when I suggested to pass
nand_pa? So now the question is, what does this address represent? Do
you have a reference manual I can look at to understand what this is?
next prev parent reply other threads:[~2020-04-30 8:37 UTC|newest]
Thread overview: 34+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-04-29 10:42 [PATCH v4 0/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-04-29 10:42 ` [PATCH v4 1/2] dt-bindings: mtd: Add YAML for Nand Flash Controller support Ramuthevar,Vadivel MuruganX
2020-04-29 15:34 ` Boris Brezillon
2020-04-30 1:07 ` Ramuthevar, Vadivel MuruganX
2020-04-29 10:42 ` [PATCH v4 2/2] mtd: rawnand: Add NAND controller support on Intel LGM SoC Ramuthevar,Vadivel MuruganX
2020-04-29 11:33 ` Boris Brezillon
2020-04-29 13:29 ` Ramuthevar, Vadivel MuruganX
2020-04-29 13:32 ` Boris Brezillon
2020-04-29 14:26 ` Ramuthevar, Vadivel MuruganX
2020-04-29 14:22 ` Boris Brezillon
2020-04-29 14:33 ` Ramuthevar, Vadivel MuruganX
2020-04-29 14:48 ` Boris Brezillon
2020-04-29 15:18 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:29 ` Ramuthevar, Vadivel MuruganX
2020-04-29 15:31 ` Boris Brezillon
2020-04-30 7:50 ` Ramuthevar, Vadivel MuruganX
2020-04-30 8:21 ` Boris Brezillon
2020-04-30 8:30 ` Ramuthevar, Vadivel MuruganX
2020-04-30 8:36 ` Boris Brezillon [this message]
2020-04-30 9:07 ` Ramuthevar, Vadivel MuruganX
2020-04-30 12:36 ` Boris Brezillon
2020-04-30 13:01 ` Boris Brezillon
2020-05-04 1:58 ` Ramuthevar, Vadivel MuruganX
2020-05-04 2:02 ` Ramuthevar, Vadivel MuruganX
2020-05-04 7:08 ` Boris Brezillon
2020-05-04 7:15 ` Ramuthevar, Vadivel MuruganX
2020-05-04 7:17 ` Boris Brezillon
2020-05-04 8:50 ` Ramuthevar, Vadivel MuruganX
2020-05-04 8:58 ` Boris Brezillon
2020-05-04 9:17 ` Ramuthevar, Vadivel MuruganX
2020-05-05 5:28 ` Ramuthevar, Vadivel MuruganX
2020-05-05 7:00 ` Boris Brezillon
2020-05-05 7:17 ` Ramuthevar, Vadivel MuruganX
2020-05-04 1:54 ` Ramuthevar, Vadivel MuruganX
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