From: Rob Herring <robh@kernel.org>
To: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
devicetree@vger.kernel.org, tsbogend@alpha.franken.de,
paulburton@kernel.org, jiaxun.yang@flygoat.com,
chenhc@lemote.com, tglx@linutronix.de, daniel.lezcano@linaro.org,
keescook@chromium.org, paul@crapouillou.net, krzk@kernel.org,
hns@goldelico.com, ebiederm@xmission.com,
dongsheng.qiu@ingenic.com, yanfei.li@ingenic.com,
rick.tyliu@ingenic.com, sernia.zhou@foxmail.com,
zhenwenjin@gmail.com
Subject: Re: [PATCH v8 4/6] dt-bindings: MIPS: Document Ingenic SoCs binding.
Date: Tue, 26 May 2020 13:29:47 -0600 [thread overview]
Message-ID: <20200526192947.GA140311@bogus> (raw)
In-Reply-To: <1589898923-60048-6-git-send-email-zhouyanjie@wanyeetech.com>
On Tue, May 19, 2020 at 10:35:21PM +0800, 周琰杰 (Zhou Yanjie) wrote:
> Document the available properties for the SoC root node and the
> CPU nodes of the devicetree for the Ingenic XBurst SoCs.
>
> Tested-by: H. Nikolaus Schaller <hns@goldelico.com>
> Tested-by: Paul Boddie <paul@boddie.org.uk>
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> ---
>
> Notes:
> v1->v2:
> Change the two Document from txt to yaml.
>
> v2->v3:
> Fix formatting errors.
>
> v3->v4:
> Fix bugs in the two yaml files.
>
> v4->v5:
> No change.
>
> v5->v6:
> Rewrite the two yaml files.
>
> v6->v7:
> 1.Update compatible strings in "ingenic,cpu.yaml".
> 2.Fix formatting errors, and enum for compatible strings.
> 3.Remove unnecessary "ingenic,soc.yaml".
>
> v7->v8:
> No change.
>
> .../bindings/mips/ingenic/ingenic,cpu.yaml | 57 ++++++++++++++++++++++
> 1 file changed, 57 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
>
> diff --git a/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
> new file mode 100644
> index 00000000..afb0207
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mips/ingenic/ingenic,cpu.yaml
> @@ -0,0 +1,57 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mips/ingenic/ingenic,cpu.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Bindings for Ingenic XBurst family CPUs
> +
> +maintainers:
> + - 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> +
> +description:
> + Ingenic XBurst family CPUs shall have the following properties.
> +
> +properties:
> + compatible:
> + oneOf:
> +
> + - description: Ingenic XBurst®1 CPU Cores
> + items:
This is a single compatible string, right? If so, drop items.
> + enum:
> + - ingenic,xburst-mxu1.0
> + - ingenic,xburst-fpu1.0-mxu1.1
> + - ingenic,xburst-fpu2.0-mxu2.0
> +
> + - description: Ingenic XBurst®2 CPU Cores
> + items:
> + enum:
> + - ingenic,xburst2-fpu2.1-mxu2.1-smt
Just: const: ingenic,xburst2-fpu2.1-mxu2.1-smt
Continuing to append CPU features isn't going to scale well. Does
'xburst2' imply certain features? If so, not really any need to have
them be explicit.
> +
> + reg:
> + maxItems: 1
> +
> +required:
> + - device_type
> + - compatible
> + - reg
> +
> +examples:
> + - |
> + cpus {
> + #address-cells = <1>;
> + #size-cells = <0>;
> +
> + cpu0: cpu@0 {
> + device_type = "cpu";
> + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
> + reg = <0>;
> + };
> +
> + cpu1: cpu@1 {
> + device_type = "cpu";
> + compatible = "ingenic,xburst-fpu1.0-mxu1.1";
> + reg = <1>;
> + };
> + };
> +...
> --
> 2.7.4
>
next prev parent reply other threads:[~2020-05-26 19:29 UTC|newest]
Thread overview: 31+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-05-19 14:35 Introduce SMP support for CI20 (based on JZ4780) v8 周琰杰 (Zhou Yanjie)
2020-05-19 14:35 ` [PATCH v8 0/6] Introduce SMP support for CI20 (based on JZ4780) 周琰杰 (Zhou Yanjie)
2020-05-19 14:35 ` [PATCH v8 1/6] MIPS: JZ4780: Introduce SMP support 周琰杰 (Zhou Yanjie)
2020-05-19 16:09 ` Paul Cercueil
2020-05-20 7:24 ` Zhou Yanjie
2020-05-19 18:21 ` kbuild test robot
2020-05-19 19:41 ` Paul Cercueil
2020-05-20 7:23 ` Zhou Yanjie
2020-05-20 11:33 ` Paul Cercueil
2020-05-20 12:32 ` Jiaxun Yang
2020-05-19 14:35 ` [PATCH v8 2/6] MIPS: CI20: Modify DTS to support high resolution timer for SMP 周琰杰 (Zhou Yanjie)
2020-05-19 14:35 ` [PATCH v8 3/6] clocksource: Ingenic: Add high resolution timer support " 周琰杰 (Zhou Yanjie)
2020-05-19 17:42 ` Paul Cercueil
2020-05-19 20:11 ` [PATCH] " Paul Cercueil
2020-05-20 22:14 ` Paul Boddie
2020-05-22 12:26 ` Paul Cercueil
2020-05-22 19:16 ` Paul Boddie
2020-05-25 23:03 ` JZ4780 LCD controller initialisation (was Re: [PATCH] clocksource: Ingenic: Add high resolution timer support for SMP.) Paul Boddie
2020-05-26 4:48 ` H. Nikolaus Schaller
2020-05-26 15:03 ` Paul Cercueil
2020-05-26 22:44 ` Paul Boddie
2020-05-26 23:07 ` Paul Cercueil
2020-06-01 20:06 ` Paul Boddie
2020-06-23 21:28 ` Paul Boddie
2020-05-19 14:35 ` [PATCH v8 4/6] dt-bindings: MIPS: Document Ingenic SoCs binding 周琰杰 (Zhou Yanjie)
2020-05-26 19:29 ` Rob Herring [this message]
2020-05-27 5:59 ` Zhou Yanjie
2020-05-19 14:35 ` [PATCH v8 5/6] MIPS: Ingenic: Add 'cpus' node for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2020-09-10 7:52 ` H. Nikolaus Schaller
2020-09-12 6:17 ` Zhou Yanjie
2020-05-19 14:35 ` [PATCH v8 6/6] MIPS: CI20: Update defconfig to support SMP 周琰杰 (Zhou Yanjie)
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