Re: [PATCH 2/6] mips: Add N64 machine type

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Mon, Jan 04, 2021 at 03:43:57PM +0200, Lauri Kasanen wrote:
> [..]
>  	select GPIOLIB
> 
> +config MACH_NINTENDO64
> +	bool "Nintendo 64 console"
> +	select CEVT_R4K
> +	select CSRC_R4K
> +	select SYS_HAS_CPU_R4300
> +	select SYS_SUPPORTS_BIG_ENDIAN
> +	select SYS_SUPPORTS_ZBOOT
> +	select SYS_SUPPORTS_32BIT_KERNEL

32BIT kernel don't compile, because you use TO_UNCAC which only
exists for 64bit kernels. One solution would be to use CKSEG1 to
convert from physical to an uncached address. But I'd prefer if
you add resources to your platform device and do ioremap in device
drivers. This way there is also no need to export the interrupt
defines outside.

> diff --git a/arch/mips/include/asm/mach-n64/irq.h b/arch/mips/include/asm/mach-n64/irq.h
> new file mode 100644
> index 0000000..4d4a1ea
> --- /dev/null
> +++ b/arch/mips/include/asm/mach-n64/irq.h
> @@ -0,0 +1,9 @@
> +/* SPDX-License-Identifier: GPL-2.0 */
> +#ifndef __ASM_MACH_N64_IRQ_H
> +#define __ASM_MACH_N64_IRQ_H
> +
> +#include <asm/n64/irq.h> /* for MIPS_CPU_IRQ_BASE */

the only thing, which should be here is the override of NR_IRQS

> +#define MIPS_CPU_IRQ_BASE	0

that's default, no need to define.

> +#define MIPS_CPU_IRQ(x)		(MIPS_CPU_IRQ_BASE + (x))
> +#define MIPS_SOFTINT0_IRQ	MIPS_CPU_IRQ(0)
> +#define MIPS_SOFTINT1_IRQ	MIPS_CPU_IRQ(1)

I doubt you need the SOFTINT defines

> +#define RCP_IRQ			MIPS_CPU_IRQ(2)
> +#define CART_IRQ		MIPS_CPU_IRQ(3)
> +#define PRENMI_IRQ		MIPS_CPU_IRQ(4)
> +#define RDBR_IRQ		MIPS_CPU_IRQ(5)
> +#define RDBW_IRQ		MIPS_CPU_IRQ(6)
> +#define TIMER_IRQ		MIPS_CPU_IRQ(7)

and this IMHO also unsed, so no need to define it.

With the approach of using a platform irq resource you don't
even need this header file as there is only a single plays,
which deals with irq assignment.

> +void __init prom_free_prom_memory(void)
> +{
> +}
> +

you can drop that now with current mips-next.

> +void __init plat_time_init(void)
> +{
> +	// 93.75 MHz cpu, count register runs at half rate

no C++ comments please.

> +	mips_hpt_frequency = 93750000 / 2;
> +}

-- 
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea.                                                [ RFC1925, 2.3 ]