From: 周琰杰 <zhouyanjie@wanyeetech.com>
To: Paul Cercueil <paul@crapouillou.net>
Cc: tsbogend@alpha.franken.de, robh+dt@kernel.org,
linux-mips@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, dongsheng.qiu@ingenic.com,
aric.pzqi@ingenic.com, rick.tyliu@ingenic.com,
sihui.liu@ingenic.com, jun.jiang@ingenic.com,
sernia.zhou@foxmail.com
Subject: Re: [PATCH v2 2/3] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs.
Date: Thu, 24 Jun 2021 12:10:46 +0800 [thread overview]
Message-ID: <20210624121046.4e1f73e1@zhouyanjie-virtual-machine> (raw)
In-Reply-To: <3L36VQ.1XFKT5OGBXT2@crapouillou.net>
Hi Paul,
于 Wed, 23 Jun 2021 19:34:15 +0100
Paul Cercueil <paul@crapouillou.net> 写道:
> Hi Zhou,
>
> Le mar., juin 22 2021 at 23:55:37 +0800, 周琰杰 (Zhou Yanjie)
> <zhouyanjie@wanyeetech.com> a écrit :
> > Add MAC syscon nodes for X1000 SoC and X1830 SoC from Ingenic.
> >
> > Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> > Acked-by: Paul Cercueil <paul@crapouillou.net>
> > ---
> >
> > Notes:
> > v1->v2:
> > No change.
> >
> > arch/mips/boot/dts/ingenic/x1000.dtsi | 7 +++++++
> > arch/mips/boot/dts/ingenic/x1830.dtsi | 7 +++++++
> > 2 files changed, 14 insertions(+)
> >
> > diff --git a/arch/mips/boot/dts/ingenic/x1000.dtsi
> > b/arch/mips/boot/dts/ingenic/x1000.dtsi
> > index aac9ded..dec7909 100644
> > --- a/arch/mips/boot/dts/ingenic/x1000.dtsi
> > +++ b/arch/mips/boot/dts/ingenic/x1000.dtsi
> > @@ -80,6 +80,11 @@
> >
> > status = "disabled";
> > };
> > +
> > + mac_phy_ctrl: mac-phy-ctrl@e8 {
> > + compatible = "syscon";
> > + reg = <0xe8 0x4>;
> > + };
>
> I acked this patch already, but you do need to update the CGU binding
> documentation as well.
Sure, I will send v3.
>
> -Paul
>
> > };
> >
> > ost: timer@12000000 {
> > @@ -347,6 +352,8 @@
> > clocks = <&cgu X1000_CLK_MAC>;
> > clock-names = "stmmaceth";
> >
> > + mode-reg = <&mac_phy_ctrl>;
> > +
> > status = "disabled";
> >
> > mdio: mdio {
> > diff --git a/arch/mips/boot/dts/ingenic/x1830.dtsi
> > b/arch/mips/boot/dts/ingenic/x1830.dtsi
> > index 59ca3a8..215257f 100644
> > --- a/arch/mips/boot/dts/ingenic/x1830.dtsi
> > +++ b/arch/mips/boot/dts/ingenic/x1830.dtsi
> > @@ -73,6 +73,11 @@
> >
> > status = "disabled";
> > };
> > +
> > + mac_phy_ctrl: mac-phy-ctrl@e8 {
> > + compatible = "syscon";
> > + reg = <0xe8 0x4>;
> > + };
> > };
> >
> > ost: timer@12000000 {
> > @@ -336,6 +341,8 @@
> > clocks = <&cgu X1830_CLK_MAC>;
> > clock-names = "stmmaceth";
> >
> > + mode-reg = <&mac_phy_ctrl>;
> > +
> > status = "disabled";
> >
> > mdio: mdio {
> > --
> > 2.7.4
> >
>
next prev parent reply other threads:[~2021-06-24 4:11 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-06-22 15:55 [PATCH v2 0/3] Misc Ingenic patches 周琰杰 (Zhou Yanjie)
2021-06-22 15:55 ` [PATCH v2 1/3] MIPS: X1830: Respect cell count of common properties 周琰杰 (Zhou Yanjie)
2021-06-22 15:55 ` [PATCH v2 2/3] MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs 周琰杰 (Zhou Yanjie)
2021-06-23 18:34 ` Paul Cercueil
2021-06-24 4:10 ` 周琰杰 [this message]
2021-06-22 15:55 ` [PATCH v2 3/3] MIPS: CI20: Add second percpu timer for SMP 周琰杰 (Zhou Yanjie)
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