From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: tsbogend@alpha.franken.de
Cc: robh@kernel.org, arnd@arndb.de, catalin.marinas@arm.com,
Liviu.Dudau@arm.com, bhelgaas@google.com, matthias.bgg@gmail.com,
gregkh@linuxfoundation.org, linux-mips@vger.kernel.org,
linux-pci@vger.kernel.org, linux-staging@lists.linux.dev,
neil@brown.name, linux-kernel@vger.kernel.org
Subject: [PATCH v2 6/6] staging: mt7621-pci: properly adjust base address for the IO window
Date: Sat, 25 Sep 2021 10:46:41 +0200 [thread overview]
Message-ID: <20210925084642.5642-7-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20210925084642.5642-1-sergio.paracuellos@gmail.com>
The value to adjust in the bridge register RALINK_PCI_IOBASE must take into
account the raw value from DT, not only the translated linux port number.
As long as io_offset is zero, the two are the same, but if you were to use
multiple host bridge in the system, or pick a different bus address in DT,
you can have a nonzero io_offset. At this means to take into account the
bus address which is used to calculate this offset, substracting it from
the IO resource start address.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
drivers/staging/mt7621-pci/pci-mt7621.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/staging/mt7621-pci/pci-mt7621.c b/drivers/staging/mt7621-pci/pci-mt7621.c
index 6acfc94a16e7..503cb1fca2e0 100644
--- a/drivers/staging/mt7621-pci/pci-mt7621.c
+++ b/drivers/staging/mt7621-pci/pci-mt7621.c
@@ -482,7 +482,7 @@ static int mt7621_pcie_enable_ports(struct pci_host_bridge *host)
/* Setup MEMWIN and IOWIN */
pcie_write(pcie, 0xffffffff, RALINK_PCI_MEMBASE);
- pcie_write(pcie, entry->res->start, RALINK_PCI_IOBASE);
+ pcie_write(pcie, entry->res->start - entry->offset, RALINK_PCI_IOBASE);
list_for_each_entry(port, &pcie->ports, list) {
if (port->enabled) {
--
2.25.1
prev parent reply other threads:[~2021-09-25 8:47 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-09-25 8:46 [PATCH v2 0/6] MIPS: ralink: fix PCI IO resources Sergio Paracuellos
2021-09-25 8:46 ` [PATCH v2 1/6] Revert "MIPS: ralink: don't define PC_IOBASE but increase IO_SPACE_LIMIT" Sergio Paracuellos
2021-09-25 8:46 ` [PATCH v2 2/6] Revert "staging: mt7621-pci: set end limit for 'ioport_resource'" Sergio Paracuellos
2021-09-25 8:46 ` [PATCH v2 3/6] MIPS: ralink: set PCI_IOBASE to 'mips_io_port_base' Sergio Paracuellos
2021-09-25 8:46 ` [PATCH v2 4/6] PCI: Allow architecture-specific pci_remap_iospace() Sergio Paracuellos
2021-09-25 8:46 ` [PATCH v2 5/6] MIPS: implement architecture-specific 'pci_remap_iospace()' Sergio Paracuellos
2021-09-25 8:46 ` Sergio Paracuellos [this message]
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