From: Stephen Boyd <sboyd@kernel.org>
To: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>,
mturquette@baylibre.com, tsbogend@alpha.franken.de
Cc: paulburton@kernel.org, paul@crapouillou.net,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-clk@vger.kernel.org
Subject: Re: [PATCH v2 2/3] clk: ingenic: Mark critical clocks in Ingenic SoCs
Date: Wed, 18 May 2022 13:57:52 -0700 [thread overview]
Message-ID: <20220518205754.8A187C385A5@smtp.kernel.org> (raw)
In-Reply-To: <20220428164454.17908-3-aidanmacdonald.0x0@gmail.com>
Quoting Aidan MacDonald (2022-04-28 09:44:53)
> Consider CPU, L2 cache, and memory clocks as critical to prevent
> them -- and the parent clocks -- from being automatically gated,
> since nothing calls clk_get() on these clocks.
>
> Gating the CPU clock hangs the processor, and gating memory makes
> external DRAM inaccessible. Normal kernel code can't hope to deal
> with either situation so those clocks have to be critical.
>
> The L2 cache is required only if caches are running, and could be
> gated if the kernel takes care to flush and disable caches before
> gating the clock. There's no mechanism to do this, and probably no
> reason to do it, so it's simpler to mark the L2 cache as critical.
>
> Signed-off-by: Aidan MacDonald <aidanmacdonald.0x0@gmail.com>
> Reviewed-by: Paul Cercueil <paul@crapouillou.net>
> ---
Applied to clk-next
next prev parent reply other threads:[~2022-05-18 20:57 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-04-28 16:44 [PATCH v2 0/3] Clock fixes for Ingenic SoCs Aidan MacDonald
2022-04-28 16:44 ` [PATCH v2 1/3] clk: ingenic: Allow specifying common clock flags Aidan MacDonald
2022-05-18 20:57 ` Stephen Boyd
2022-04-28 16:44 ` [PATCH v2 2/3] clk: ingenic: Mark critical clocks in Ingenic SoCs Aidan MacDonald
2022-05-18 20:57 ` Stephen Boyd [this message]
2022-04-28 16:44 ` [PATCH v2 3/3] mips: ingenic: Do not manually reference the CPU clock Aidan MacDonald
2022-05-18 20:58 ` Stephen Boyd
2022-05-09 9:12 ` [PATCH v2 0/3] Clock fixes for Ingenic SoCs 周琰杰
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