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References: <20220419051114.1569291-1-seanga2@gmail.com> <d92dd996-6961-5291-9504-1fe284b40dd6@gmail.com>
Subject: Re: [RFT PATCH] clk: ls1c: Fix PLL rate calculation
From:   Stephen Boyd <sboyd@kernel.org>
Cc:     linux-kernel@vger.kernel.org,
        Keguang Zhang <keguang.zhang@gmail.com>,
        Du Huanpeng <dhu@hodcarrier.org>,
        Yang Ling <gnaygnil@gmail.com>
To:     Sean Anderson <seanga2@gmail.com>, linux-clk@vger.kernel.org,
        linux-mips@vger.kernel.org
Date:   Tue, 09 Aug 2022 11:06:58 -0700
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Quoting Sean Anderson (2022-08-03 16:28:41)
> On 4/19/22 1:11 AM, Sean Anderson wrote:
> >  =20
> >       pll =3D __raw_readl(LS1X_CLK_PLL_FREQ);
> > -     rate =3D ((pll >> 8) & 0xff) + ((pll >> 16) & 0xff);
> > +     rate =3D (pll & 0xff00) + ((pll >> 16) & 0xff);
> >       rate *=3D OSC;
> > -     rate >>=3D 2;
> > +     rate >>=3D 10;
> >  =20
> >       return rate;
> >   }
> >=20
>=20
> Since there have been no objections, can we apply this?
>=20

Can you resend it? I can apply it after the merge window closes next
week.