From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id A8803C6FA8B for ; Mon, 12 Sep 2022 14:02:59 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230014AbiILOC6 (ORCPT ); Mon, 12 Sep 2022 10:02:58 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230008AbiILOCy (ORCPT ); Mon, 12 Sep 2022 10:02:54 -0400 Received: from elvis.franken.de (elvis.franken.de [193.175.24.41]) by lindbergh.monkeyblade.net (Postfix) with ESMTP id 3746932AB9; Mon, 12 Sep 2022 07:02:46 -0700 (PDT) Received: from uucp (helo=alpha) by elvis.franken.de with local-bsmtp (Exim 3.36 #1) id 1oXk1M-0007Yg-04; Mon, 12 Sep 2022 16:02:44 +0200 Received: by alpha.franken.de (Postfix, from userid 1000) id 0D555C1291; Mon, 12 Sep 2022 16:02:34 +0200 (CEST) Date: Mon, 12 Sep 2022 16:02:34 +0200 From: Thomas Bogendoerfer To: Aleksander Bajkowski Cc: Martin Blumenstingl , Marc Zyngier , Sander Vanheule , Hauke Mehrtens , git@birger-koblitz.de, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] MIPS: smp-mt: enable all hardware interrupts on second VPE Message-ID: <20220912140233.GA9366@alpha.franken.de> References: <20220702190705.5319-1-olek2@wp.pl> <3c9a032edd0fb9b9608ad3ca08d6e3cc38f21464.camel@svanheule.net> <87fsjen2kl.wl-maz@kernel.org> <20220706081901.GA10797@alpha.franken.de> <20220707100630.GC9894@alpha.franken.de> <20220707143930.GA14693@alpha.franken.de> <794a2039-cdf7-2676-482f-9913a8949647@wp.pl> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <794a2039-cdf7-2676-482f-9913a8949647@wp.pl> User-Agent: Mutt/1.10.1 (2018-07-13) Precedence: bulk List-ID: X-Mailing-List: linux-mips@vger.kernel.org On Sat, Sep 10, 2022 at 12:53:40PM +0200, Aleksander Bajkowski wrote: > Hi THomas, > > On 7/7/22 16:39, Thomas Bogendoerfer wrote: > [...] > >> Or can you point me to the code in > >> drivers/irqchip/irq-mips-cpu.c that's responsible for enabling the > >> interrupts on VPE 1 (is it simply unmask_mips_irq)? > > > > IMHO there is the problem, irq-mips-cpu.c can only do CPU irq operations > > on the same CPU. I've checked MIPS MT specs and it's possible do > > modify CP0 registers between VPEs. Using that needs changes in > > irq-mips-cpu.c. But mabye that's not woth the effort as probably > > all SMP cabable platforms have some multi processort capable > > interrupt controller implemented. > > > > I thought about another way solve the issue. By introducing a > > new function in smp-mt.c which sets the value of the interrupt > > mask for the secondary CPU, which is then used in vsmp_init_secondary(). > > Not sure if this is worth the effort compared to a .boot_secondary > > override. > > > Enabling interrupts on the second VPE using hotplug will be accepted > upstream? Below is a sample patch. as this is just another hack, below is what I prefer. Thomas. commit 15853dc9e6d213558acbf961f98e9f77b4b61db2 Author: Thomas Bogendoerfer Date: Mon Sep 12 15:59:44 2022 +0200 my lantiq approach diff --git a/arch/mips/lantiq/prom.c b/arch/mips/lantiq/prom.c index c731082a0c42..1cc4f56b57f6 100644 --- a/arch/mips/lantiq/prom.c +++ b/arch/mips/lantiq/prom.c @@ -84,6 +84,16 @@ void __init plat_mem_setup(void) __dt_setup_arch(dtb); } +#if defined(CONFIG_MIPS_MT_SMP) +extern const struct plat_smp_ops vsmp_smp_ops; +static struct plat_smp_ops lantiq_smp_ops; + +static void lantiq_init_secondary(void) +{ + set_c0_status(ST0_IM); +} +#endif + void __init prom_init(void) { /* call the soc specific detetcion code and get it to fill soc_info */ @@ -95,7 +105,13 @@ void __init prom_init(void) prom_init_cmdline(); #if defined(CONFIG_MIPS_MT_SMP) - if (register_vsmp_smp_ops()) + + if (cpu_has_mipsmt) { + lantiq_smp_ops = vsmp_smp_ops; + lantiq_smp_ops.init_secondary = lantiq_init_secondary; + register_smp_ops(&lantiq_smp_ops); + } else { panic("failed to register_vsmp_smp_ops()"); + } #endif } -- Crap can work. Given enough thrust pigs will fly, but it's not necessarily a good idea. [ RFC1925, 2.3 ]