Re: [PATCH 2/2] MIPS: cevt-r4k: Offset counter value for clearing compare interrupt

[Thomas Bogendoerfer <tsbogend@alpha.franken.de>]

On Sat, Feb 25, 2023 at 10:10:08PM +0000, Jiaxun Yang wrote:
> In c0_compare_int_usable we clear compare interrupt by write value
> just read out from counter to compare register.
> 
> However sometimes if those all instructions are graduated together
> then it's possible that at the time compare register is written, the
> counter haven't progressed, thus the interrupt is triggered again.
> 
> It also applies to QEMU that instructions is execuated significantly
> faster then counter.
> 
> Offset the counter value a litlle bit to prevent that happen.
> 
> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
> ---
>  arch/mips/kernel/cevt-r4k.c | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/arch/mips/kernel/cevt-r4k.c b/arch/mips/kernel/cevt-r4k.c
> index 32ec67c9ab67..bbc422376e97 100644
> --- a/arch/mips/kernel/cevt-r4k.c
> +++ b/arch/mips/kernel/cevt-r4k.c
> @@ -200,6 +200,8 @@ int c0_compare_int_usable(void)
>  	 */
>  	if (c0_compare_int_pending()) {
>  		cnt = read_c0_count();
> +		// Drawdown a little bit in case counter haven't progressed

no C++ comments

> +		cnt -= COMPARE_INT_SEEN_TICKS;
>  		write_c0_compare(cnt);
>  		back_to_back_c0_hazard();
>  		while (read_c0_count() < (cnt  + COMPARE_INT_SEEN_TICKS))

this doesn't make sense. clearing of the interrupts happes because of
this loop. So either COMPARE_INT_SEEN_TICKS is too small or you are
hunting a different bug.

Thomas.

-- 
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