From: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Jiaxun Yang <jiaxun.yang@flygoat.com>
Cc: "linux-mips@vger.kernel.org" <linux-mips@vger.kernel.org>
Subject: Re: [PATCH 2/2] MIPS: cevt-r4k: Offset counter value for clearing compare interrupt
Date: Mon, 27 Feb 2023 17:48:36 +0100 [thread overview]
Message-ID: <20230227164836.GA17414@alpha.franken.de> (raw)
In-Reply-To: <1386E355-383C-464E-9821-34BA8ED4DCE3@flygoat.com>
On Mon, Feb 27, 2023 at 11:44:48AM +0000, Jiaxun Yang wrote:
> > so not seen on real hardware ?
>
> It was discovered on FPGA and then I tried to debug with simulation to
> reveal what’s going on hardware side.
ic, I think the best fix would be to do a write_c0_compare(cnt - 1).
Subtracting COMPARE_INT_SEEN_TICKS feels like overkill to me.
Thomas.
--
Crap can work. Given enough thrust pigs will fly, but it's not necessarily a
good idea. [ RFC1925, 2.3 ]
prev parent reply other threads:[~2023-02-27 16:49 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-02-25 22:10 [PATCH 0/2] MIPS Booting fixes Jiaxun Yang
2023-02-25 22:10 ` [PATCH 1/2] MIPS: smp-cps: Don't rely on CP0_CMGCRBASE Jiaxun Yang
2023-02-27 11:59 ` Thomas Bogendoerfer
2023-02-25 22:10 ` [PATCH 2/2] MIPS: cevt-r4k: Offset counter value for clearing compare interrupt Jiaxun Yang
2023-02-26 22:04 ` Philippe Mathieu-Daudé
2023-02-26 23:23 ` Thomas Bogendoerfer
2023-02-27 1:22 ` Jiaxun Yang
2023-02-27 9:31 ` Thomas Bogendoerfer
2023-02-27 11:44 ` Jiaxun Yang
2023-02-27 16:48 ` Thomas Bogendoerfer [this message]
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