From: Sergio Paracuellos <sergio.paracuellos@gmail.com>
To: linux-clk@vger.kernel.org
Cc: linux-mips@vger.kernel.org, tsbogend@alpha.franken.de,
john@phrozen.org, linux-kernel@vger.kernel.org,
p.zabel@pengutronix.de, mturquette@baylibre.com,
sboyd@kernel.org, robh+dt@kernel.org,
krzysztof.kozlowski+dt@linaro.org, matthias.bgg@gmail.com,
devicetree@vger.kernel.org, arinc.unal@arinc9.com,
yangshiji66@outlook.com
Subject: [PATCH v5 3/9] mips: ralink: rt288x: remove clock related code
Date: Mon, 19 Jun 2023 06:09:35 +0200 [thread overview]
Message-ID: <20230619040941.1340372-4-sergio.paracuellos@gmail.com> (raw)
In-Reply-To: <20230619040941.1340372-1-sergio.paracuellos@gmail.com>
A properly clock driver for ralink SoCs has been added. Hence there is no
need to have clock related code in 'arch/mips/ralink' folder anymore.
Signed-off-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
---
arch/mips/include/asm/mach-ralink/rt288x.h | 10 -------
arch/mips/ralink/rt288x.c | 31 ----------------------
2 files changed, 41 deletions(-)
diff --git a/arch/mips/include/asm/mach-ralink/rt288x.h b/arch/mips/include/asm/mach-ralink/rt288x.h
index 66a999cd1d80..66d190358e3a 100644
--- a/arch/mips/include/asm/mach-ralink/rt288x.h
+++ b/arch/mips/include/asm/mach-ralink/rt288x.h
@@ -18,7 +18,6 @@
#define SYSC_REG_CHIP_NAME1 0x04
#define SYSC_REG_CHIP_ID 0x0c
#define SYSC_REG_SYSTEM_CONFIG 0x10
-#define SYSC_REG_CLKCFG 0x30
#define RT2880_CHIP_NAME0 0x38325452
#define RT2880_CHIP_NAME1 0x20203038
@@ -27,15 +26,6 @@
#define CHIP_ID_ID_SHIFT 8
#define CHIP_ID_REV_MASK 0xff
-#define SYSTEM_CONFIG_CPUCLK_SHIFT 20
-#define SYSTEM_CONFIG_CPUCLK_MASK 0x3
-#define SYSTEM_CONFIG_CPUCLK_250 0x0
-#define SYSTEM_CONFIG_CPUCLK_266 0x1
-#define SYSTEM_CONFIG_CPUCLK_280 0x2
-#define SYSTEM_CONFIG_CPUCLK_300 0x3
-
-#define CLKCFG_SRAM_CS_N_WDT BIT(9)
-
#define RT2880_SDRAM_BASE 0x08000000
#define RT2880_MEM_SIZE_MIN 2
#define RT2880_MEM_SIZE_MAX 128
diff --git a/arch/mips/ralink/rt288x.c b/arch/mips/ralink/rt288x.c
index 456ba0b2599e..0c6a87452dd1 100644
--- a/arch/mips/ralink/rt288x.c
+++ b/arch/mips/ralink/rt288x.c
@@ -21,37 +21,6 @@
static struct ralink_soc_info *soc_info_ptr;
-void __init ralink_clk_init(void)
-{
- unsigned long cpu_rate, wmac_rate = 40000000;
- u32 t = rt_sysc_r32(SYSC_REG_SYSTEM_CONFIG);
- t = ((t >> SYSTEM_CONFIG_CPUCLK_SHIFT) & SYSTEM_CONFIG_CPUCLK_MASK);
-
- switch (t) {
- case SYSTEM_CONFIG_CPUCLK_250:
- cpu_rate = 250000000;
- break;
- case SYSTEM_CONFIG_CPUCLK_266:
- cpu_rate = 266666667;
- break;
- case SYSTEM_CONFIG_CPUCLK_280:
- cpu_rate = 280000000;
- break;
- case SYSTEM_CONFIG_CPUCLK_300:
- cpu_rate = 300000000;
- break;
- }
-
- ralink_clk_add("cpu", cpu_rate);
- ralink_clk_add("300100.timer", cpu_rate / 2);
- ralink_clk_add("300120.watchdog", cpu_rate / 2);
- ralink_clk_add("300500.uart", cpu_rate / 2);
- ralink_clk_add("300900.i2c", cpu_rate / 2);
- ralink_clk_add("300c00.uartlite", cpu_rate / 2);
- ralink_clk_add("400000.ethernet", cpu_rate / 2);
- ralink_clk_add("480000.wmac", wmac_rate);
-}
-
void __init ralink_of_remap(void)
{
rt_sysc_membase = plat_of_remap_node("ralink,rt2880-sysc");
--
2.25.1
next prev parent reply other threads:[~2023-06-19 4:10 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-19 4:09 [PATCH v5 0/9] mips: ralink: add complete clock and reset driver for mtmips SoCs Sergio Paracuellos
2023-06-19 4:09 ` [PATCH v5 1/9] dt-bindings: clock: add mtmips SoCs system controller Sergio Paracuellos
2023-06-19 4:09 ` [PATCH v5 2/9] clk: ralink: add clock and reset driver for MTMIPS SoCs Sergio Paracuellos
2023-06-19 4:09 ` Sergio Paracuellos [this message]
2023-06-19 4:09 ` [PATCH v5 4/9] mips: ralink: rt305x: remove clock related code Sergio Paracuellos
2023-06-19 4:09 ` [PATCH v5 5/9] mips: ralink: rt3883: " Sergio Paracuellos
2023-06-19 4:09 ` [PATCH v5 6/9] mips: ralink: mt7620: " Sergio Paracuellos
2023-06-19 4:09 ` [PATCH v5 7/9] mips: ralink: remove reset " Sergio Paracuellos
2023-06-19 4:09 ` [PATCH v5 8/9] mips: ralink: get cpu rate from new driver code Sergio Paracuellos
2023-06-19 4:09 ` [PATCH v5 9/9] MAINTAINERS: add Mediatek MTMIPS Clock maintainer Sergio Paracuellos
2023-06-21 14:07 ` [PATCH v5 0/9] mips: ralink: add complete clock and reset driver for mtmips SoCs Thomas Bogendoerfer
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