From: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Paul Burton <paulburton@kernel.org>,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
linux-mips@vger.kernel.org, Jiaxun Yang <jiaxun.yang@flygoat.com>,
Rob Herring <robh+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Cc: "Vladimir Kondratiev" <vladimir.kondratiev@mobileye.com>,
"Tawfik Bayouk" <tawfik.bayouk@mobileye.com>,
"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
"Théo Lebrun" <theo.lebrun@bootlin.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>
Subject: [PATCH v2 10/21] MIPS: Avoid unnecessary reservation of exception space
Date: Thu, 23 Nov 2023 16:26:27 +0100 [thread overview]
Message-ID: <20231123152639.561231-11-gregory.clement@bootlin.com> (raw)
In-Reply-To: <20231123152639.561231-1-gregory.clement@bootlin.com>
From: Jiaxun Yang <jiaxun.yang@flygoat.com>
Nowadays we allocate exception base from memblock for r2_r6,
so we don't need to reverse exception space at the start of
the memory for r2_r6 processors.
For older processors the reservation is moved to traps_init
where we have knowledge of exact size we need. We also add
a sanity check to detect possible overlap with kernel.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/include/asm/traps.h | 1 -
arch/mips/kernel/cpu-probe.c | 5 -----
arch/mips/kernel/cpu-r3k-probe.c | 2 --
arch/mips/kernel/traps.c | 12 +++++++-----
4 files changed, 7 insertions(+), 13 deletions(-)
diff --git a/arch/mips/include/asm/traps.h b/arch/mips/include/asm/traps.h
index 15cde638b4070..d3dddd1c083a9 100644
--- a/arch/mips/include/asm/traps.h
+++ b/arch/mips/include/asm/traps.h
@@ -24,7 +24,6 @@ extern void (*board_ebase_setup)(void);
extern void (*board_cache_error_setup)(void);
extern int register_nmi_notifier(struct notifier_block *nb);
-extern void reserve_exception_space(phys_addr_t addr, unsigned long size);
extern char except_vec_nmi[];
#define VECTORSPACING 0x100 /* for EI/VI mode */
diff --git a/arch/mips/kernel/cpu-probe.c b/arch/mips/kernel/cpu-probe.c
index b406d8bfb15a3..54e8b0fd4a2ab 100644
--- a/arch/mips/kernel/cpu-probe.c
+++ b/arch/mips/kernel/cpu-probe.c
@@ -1570,7 +1570,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
c->cputype = CPU_BMIPS3300;
__cpu_name[cpu] = "Broadcom BMIPS3300";
set_elf_platform(cpu, "bmips3300");
- reserve_exception_space(0x400, VECTORSPACING * 64);
break;
case PRID_IMP_BMIPS43XX: {
int rev = c->processor_id & PRID_REV_MASK;
@@ -1581,7 +1580,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "Broadcom BMIPS4380";
set_elf_platform(cpu, "bmips4380");
c->options |= MIPS_CPU_RIXI;
- reserve_exception_space(0x400, VECTORSPACING * 64);
} else {
c->cputype = CPU_BMIPS4350;
__cpu_name[cpu] = "Broadcom BMIPS4350";
@@ -1598,7 +1596,6 @@ static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu)
__cpu_name[cpu] = "Broadcom BMIPS5000";
set_elf_platform(cpu, "bmips5000");
c->options |= MIPS_CPU_ULRI | MIPS_CPU_RIXI;
- reserve_exception_space(0x1000, VECTORSPACING * 64);
break;
}
}
@@ -1996,8 +1993,6 @@ void cpu_probe(void)
if (cpu == 0)
__ua_limit = ~((1ull << cpu_vmbits) - 1);
#endif
-
- reserve_exception_space(0, 0x1000);
}
void cpu_report(void)
diff --git a/arch/mips/kernel/cpu-r3k-probe.c b/arch/mips/kernel/cpu-r3k-probe.c
index be93469c0e0ec..05410b743e571 100644
--- a/arch/mips/kernel/cpu-r3k-probe.c
+++ b/arch/mips/kernel/cpu-r3k-probe.c
@@ -137,8 +137,6 @@ void cpu_probe(void)
cpu_set_fpu_opts(c);
else
cpu_set_nofpu_opts(c);
-
- reserve_exception_space(0, 0x400);
}
void cpu_report(void)
diff --git a/arch/mips/kernel/traps.c b/arch/mips/kernel/traps.c
index 651c9ec6265a9..b6e94654f6211 100644
--- a/arch/mips/kernel/traps.c
+++ b/arch/mips/kernel/traps.c
@@ -2007,10 +2007,6 @@ unsigned long exception_handlers[32];
static unsigned long vi_vecbase;
unsigned long vi_handlers[64];
-void reserve_exception_space(phys_addr_t addr, unsigned long size)
-{
- memblock_reserve(addr, size);
-}
void __init *set_except_vector(int n, void *addr)
{
@@ -2394,7 +2390,13 @@ void __init trap_init(void)
}
if (!cpu_has_mips_r2_r6) {
- ebase = CAC_BASE;
+ ebase_pa = 0x0;
+ ebase = CKSEG0ADDR(ebase_pa);
+
+ if (__pa_symbol(_stext) < (ebase_pa + vec_size))
+ pr_err("Insufficient space for exception vectors\n");
+
+ memblock_reserve(ebase_pa, vec_size);
} else {
vec_size = max(vec_size, PAGE_SIZE);
ebase_pa = memblock_phys_alloc(vec_size, 1 << fls(vec_size));
--
2.42.0
next prev parent reply other threads:[~2023-11-23 15:27 UTC|newest]
Thread overview: 36+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-11-23 15:26 [PATCH v2 00/21] Add support for the Mobileye EyeQ5 SoC Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 01/21] MIPS: compressed: Use correct instruction for 64 bit code Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 02/21] MIPS: Export higher/highest relocation functions in uasm Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 03/21] MIPS: spaces: Define a couple of handy macros Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 04/21] MIPS: genex: Fix except_vec_vi for kernel in XKPHYS Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 05/21] MIPS: Fix set_uncached_handler for ebase " Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 06/21] MIPS: Refactor mips_cps_core_entry implementation Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 07/21] MIPS: Fix cache issue with mips_cps_core_entry Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 08/21] MIPS: Allow kernel base to be set from Kconfig for all platforms Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 09/21] MIPS: traps: Handle CPU with non standard vint offset Gregory CLEMENT
2023-11-23 15:26 ` Gregory CLEMENT [this message]
2023-11-23 15:26 ` [PATCH v2 11/21] MIPS: traps: Enhance memblock ebase allocation process Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 12/21] MIPS: Get rid of CONFIG_NO_EXCEPT_FILL Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 13/21] MIPS: traps: Give more explanations if ebase doesn't belong to KSEG0 Gregory CLEMENT
2023-11-26 11:31 ` kernel test robot
2023-11-23 15:26 ` [PATCH v2 14/21] dt-bindings: Add vendor prefix for Mobileye Vision Technologies Ltd Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 15/21] dt-bindings: mips: cpu: Add I-Class I6500 Multiprocessor Core Gregory CLEMENT
2023-11-24 8:25 ` Krzysztof Kozlowski
2023-11-30 10:51 ` Gregory CLEMENT
2023-11-30 12:00 ` Krzysztof Kozlowski
2023-11-24 11:37 ` Serge Semin
2023-11-23 15:26 ` [PATCH v2 16/21] dt-bindings: mips: Add bindings for Mobileye SoCs Gregory CLEMENT
2023-11-23 16:57 ` Rob Herring
2023-11-26 18:57 ` Rob Herring
2023-11-23 15:26 ` [PATCH v2 17/21] dt-bindings: mfd: syscon: Document EyeQ5 OLB Gregory CLEMENT
2023-11-24 8:25 ` Krzysztof Kozlowski
2023-11-23 15:26 ` [PATCH v2 18/21] MIPS: mobileye: Add EyeQ5 dtsi Gregory CLEMENT
2023-11-24 8:27 ` Krzysztof Kozlowski
2023-12-01 10:56 ` Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 19/21] MIPS: mobileye: Add EPM5 device tree Gregory CLEMENT
2023-11-23 15:26 ` [PATCH v2 20/21] MIPS: generic: Add support for Mobileye EyeQ5 Gregory CLEMENT
2023-11-23 17:46 ` Jiaxun Yang
2023-12-01 10:34 ` Gregory CLEMENT
2023-12-01 10:49 ` Jiaxun Yang
2023-11-23 15:26 ` [PATCH v2 21/21] MAINTAINERS: Add entry for Mobileye MIPS SoCs Gregory CLEMENT
2023-11-23 17:31 ` [PATCH v2 00/21] Add support for the Mobileye EyeQ5 SoC Jiaxun Yang
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