Re: [PATCH v2 18/21] MIPS: mobileye: Add EyeQ5 dtsi

Krzysztof Kozlowski
2023-11-24T08:27:46Z

On 23/11/2023 16:26, Gregory CLEMENT wrote:
> Add a device tree include file for the Mobileye EyeQ5 SoC.
>
> Based on the work of Slava Samsonov <stanislav.samsonov@intel.com>
>
> Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
> ---

> + aliases {
> + serial0 = &uart0;
> + serial1 = &uart1;
> + serial2 = &uart2;
> + };
> +
> + cpu_intc: interrupt-controller {
> + compatible = "mti,cpu-interrupt-controller";
> + interrupt-controller;
> + #address-cells = <0>;
> + #interrupt-cells = <1>;
> + };
> +
> + gic: interrupt-controller@140000 {

Why do you put MMIO nodes in top-level?

> + compatible = "mti,gic";
> + reg = <0x0 0x140000 0x0 0x20000>;
> + interrupt-controller;
> + #interrupt-cells = <3>;
> +
> + /*
> + * Declare the interrupt-parent even though the mti,gic
> + * binding doesn't require it, such that the kernel can
> + * figure out that cpu_intc is the root interrupt
> + * controller & should be probed first.
> + */
> + interrupt-parent = <&cpu_intc>;
> +
> + timer {
> + compatible = "mti,gic-timer";
> + interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
> + clocks = <&core0_clk>;
> + };
> + };
> +
> + soc: soc {

Are you sure dtbs_check W=1 does not complain? I think you miss here
address.

> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges;
> + compatible = "simple-bus";
> +
> + uart0: serial@800000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0 0x800000 0x0 0x1000>;
> + reg-io-width = <4>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_clk>, <&occ_periph>;
> + clock-names = "uartclk", "apb_pclk";
> + };
> +
> + uart1: serial@900000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0 0x900000 0x0 0x1000>;
> + reg-io-width = <4>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_clk>, <&occ_periph>;
> + clock-names = "uartclk", "apb_pclk";
> + };
> +
> + uart2: serial@a00000 {
> + compatible = "arm,pl011", "arm,primecell";
> + reg = <0 0xa00000 0x0 0x1000>;
> + reg-io-width = <4>;
> + interrupt-parent = <&gic>;
> + interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
> + clocks = <&uart_clk>, <&occ_periph>;
> + clock-names = "uartclk", "apb_pclk";
> + };
> +
> + olb: olb@e00000 {
> + compatible = "mobileye,eyeq5-olb", "syscon", "simple-mfd";
> + reg = <0 0xe00000 0x0 0x400>;
> + reg-io-width = <4>;
> + };
> +

Stray blank line.

> + };
> +};

Best regards,
Krzysztof