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Tue, 7 May 2024 05:01:53 -0400 (EDT) From: Jiaxun Yang Date: Tue, 07 May 2024 10:01:50 +0100 Subject: [PATCH 2/5] MIPS: cm: Prefix probe functions with __init Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <20240507-cm_probe-v1-2-11dbfd598f3c@flygoat.com> References: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> In-Reply-To: <20240507-cm_probe-v1-0-11dbfd598f3c@flygoat.com> To: Paul Burton , Thomas Bogendoerfer , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Jiaxun Yang X-Mailer: b4 0.13.0 X-Developer-Signature: v=1; a=openpgp-sha256; l=2498; i=jiaxun.yang@flygoat.com; h=from:subject:message-id; bh=SLgeVPAUIVYffojO40aOD2FkVjz1kvjwA4zqDsv9YXo=; b=owGbwMvMwCHmXMhTe71c8zDjabUkhjTLt/879SpaDhjy57Cr8bNKrrRfcsLQzVh4Tde5wOZ/9 zXPuFt2lLIwiHEwyIopsoQIKPVtaLy44PqDrD8wc1iZQIYwcHEKwEQ2LWJk2Nt6utjdSyU+ZtX3 FPWrzwLKneclqbxxvvXvgKST4AGvewy/WY2VJixl5Jp9xfBty882MdXy1INV9R2r+99GnbcNFTT iAwA= X-Developer-Key: i=jiaxun.yang@flygoat.com; a=openpgp; fpr=980379BEFEBFBF477EA04EF9C111949073FC0F67 Those functions are only used at boot time. Prefix them with __init so they can be discarded after boot. Signed-off-by: Jiaxun Yang --- arch/mips/include/asm/mips-cm.h | 4 ++-- arch/mips/kernel/mips-cm.c | 8 ++++---- 2 files changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/mips/include/asm/mips-cm.h b/arch/mips/include/asm/mips-cm.h index c2930a75b7e4..5292b516d60b 100644 --- a/arch/mips/include/asm/mips-cm.h +++ b/arch/mips/include/asm/mips-cm.h @@ -30,7 +30,7 @@ extern void __iomem *mips_cm_l2sync_base; * and may be overridden by platforms which determine this address in a * different way by defining a function with the same prototype. */ -extern phys_addr_t mips_cm_phys_base(void); +extern phys_addr_t __init mips_cm_phys_base(void); /** * mips_cm_l2sync_phys_base - retrieve the physical base address of the CM @@ -43,7 +43,7 @@ extern phys_addr_t mips_cm_phys_base(void); * determine this address in a different way by defining a function with the * same prototype. */ -extern phys_addr_t mips_cm_l2sync_phys_base(void); +extern phys_addr_t __init mips_cm_l2sync_phys_base(void); /* * mips_cm_is64 - determine CM register width diff --git a/arch/mips/kernel/mips-cm.c b/arch/mips/kernel/mips-cm.c index 3a115fab5573..dddc9428fe58 100644 --- a/arch/mips/kernel/mips-cm.c +++ b/arch/mips/kernel/mips-cm.c @@ -179,7 +179,7 @@ static char *cm3_causes[32] = { static DEFINE_PER_CPU_ALIGNED(spinlock_t, cm_core_lock); static DEFINE_PER_CPU_ALIGNED(unsigned long, cm_core_lock_flags); -phys_addr_t __weak mips_cm_phys_base(void) +phys_addr_t __init __weak mips_cm_phys_base(void) { unsigned long cmgcr; @@ -198,7 +198,7 @@ phys_addr_t __weak mips_cm_phys_base(void) return (cmgcr & MIPS_CMGCRF_BASE) << (36 - 32); } -phys_addr_t __weak mips_cm_l2sync_phys_base(void) +phys_addr_t __init __weak mips_cm_l2sync_phys_base(void) { u32 base_reg; @@ -214,7 +214,7 @@ phys_addr_t __weak mips_cm_l2sync_phys_base(void) return mips_cm_phys_base() + MIPS_CM_GCR_SIZE; } -static void mips_cm_probe_l2sync(void) +static void __init mips_cm_probe_l2sync(void) { unsigned major_rev; phys_addr_t addr; @@ -237,7 +237,7 @@ static void mips_cm_probe_l2sync(void) mips_cm_l2sync_base = ioremap(addr, MIPS_CM_L2SYNC_SIZE); } -int mips_cm_probe(void) +int __init mips_cm_probe(void) { phys_addr_t addr; u32 base_reg; -- 2.34.1