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From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
	 Serge Semin <fancer.lancer@gmail.com>,
	 Daniel Lezcano <daniel.lezcano@linaro.org>,
	 Thomas Gleixner <tglx@linutronix.de>
Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
	 Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [PATCH 4/7] MIPS: csrc-r4k: Don't register as sched_clock if unfit
Date: Sat, 11 May 2024 17:00:11 +0100	[thread overview]
Message-ID: <20240511-mips-clks-v1-4-ddb4a10ee9f9@flygoat.com> (raw)
In-Reply-To: <20240511-mips-clks-v1-0-ddb4a10ee9f9@flygoat.com>

When we have more than one CPU in system, counter synchronisation
overhead can lead to a scenario that sched_clock goes backward when
being read from different CPUs.

This is accommodated by CONFIG_HAVE_UNSTABLE_SCHED_CLOCK, but it's
unavailable on 32bit kernel.

We don't want to risk sched_clock correctness, so if we have multiple
CPU in system and CONFIG_HAVE_UNSTABLE_SCHED_CLOCK is not set, we just
don't use counter as sched_clock source.

Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
 arch/mips/kernel/csrc-r4k.c | 17 ++++++++++++++---
 1 file changed, 14 insertions(+), 3 deletions(-)

diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index 5c37e41e8970..18733a2ec594 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -68,6 +68,18 @@ static bool rdhwr_count_usable(void)
 	return false;
 }
 
+static inline __init bool count_can_be_sched_clock(void)
+{
+	if (IS_ENABLED(CONFIG_CPU_FREQ))
+		return false;
+
+	if (num_possible_cpus() > 1 &&
+			!IS_ENABLED(CONFIG_HAVE_UNSTABLE_SCHED_CLOCK))
+		return false;
+
+	return true;
+}
+
 #ifdef CONFIG_CPU_FREQ
 
 static bool __read_mostly r4k_clock_unstable;
@@ -125,9 +137,8 @@ int __init init_r4k_clocksource(void)
 
 	clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
 
-#ifndef CONFIG_CPU_FREQ
-	sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency);
-#endif
+	if (count_can_be_sched_clock())
+		sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency);
 
 	return 0;
 }

-- 
2.34.1


  parent reply	other threads:[~2024-05-11 16:00 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-05-11 16:00 [PATCH 0/7] MIPS: clocksource cumulative enhancements Jiaxun Yang
2024-05-11 16:00 ` [PATCH 1/7] MIPS: csrc-r4k: Refine rating computation Jiaxun Yang
2024-06-01 22:23   ` Maciej W. Rozycki
2024-05-11 16:00 ` [PATCH 2/7] MIPS: csrc-r4k: Apply verification clocksource flags Jiaxun Yang
2024-05-11 16:00 ` [PATCH 3/7] MIPS: csrc-r4k: Select HAVE_UNSTABLE_SCHED_CLOCK if 64BIT Jiaxun Yang
2024-06-01 22:30   ` Maciej W. Rozycki
2024-06-04 14:51     ` Jiaxun Yang
2024-05-11 16:00 ` Jiaxun Yang [this message]
2024-05-11 16:00 ` [PATCH 5/7] MIPS: sync-r4k: Rework based on x86 tsc_sync Jiaxun Yang
2024-05-11 16:00 ` [PATCH 6/7] clocksource: mips-gic-timer: Refine rating computation Jiaxun Yang
2024-05-11 16:00 ` [PATCH 7/7] clocksource: mips-gic-timer: Correct sched_clock width Jiaxun Yang
2024-05-27 12:24   ` Philippe Mathieu-Daudé

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