From: Jiaxun Yang <jiaxun.yang@flygoat.com>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Serge Semin <fancer.lancer@gmail.com>,
Daniel Lezcano <daniel.lezcano@linaro.org>,
Thomas Gleixner <tglx@linutronix.de>
Cc: "Maciej W. Rozycki" <macro@orcam.me.uk>,
linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org,
Jiaxun Yang <jiaxun.yang@flygoat.com>
Subject: [PATCH v2 4/7] MIPS: csrc-r4k: Don't register as sched_clock if unfit
Date: Wed, 12 Jun 2024 09:54:31 +0100 [thread overview]
Message-ID: <20240612-mips-clks-v2-4-a57e6f49f3db@flygoat.com> (raw)
In-Reply-To: <20240612-mips-clks-v2-0-a57e6f49f3db@flygoat.com>
When we have more than one CPU in system, counter synchronisation
overhead can lead to a scenario that sched_clock goes backward when
being read from different CPUs.
This is accommodated by CONFIG_HAVE_UNSTABLE_SCHED_CLOCK, but it's
unavailable on 32bit kernel.
We don't want to risk sched_clock correctness, so if we have multiple
CPU in system and CONFIG_HAVE_UNSTABLE_SCHED_CLOCK is not set, we just
don't use counter as sched_clock source.
Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
---
arch/mips/kernel/csrc-r4k.c | 17 ++++++++++++++---
1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/arch/mips/kernel/csrc-r4k.c b/arch/mips/kernel/csrc-r4k.c
index 055747a7417d..bdb1fa8931f4 100644
--- a/arch/mips/kernel/csrc-r4k.c
+++ b/arch/mips/kernel/csrc-r4k.c
@@ -68,6 +68,18 @@ static bool rdhwr_count_usable(void)
return false;
}
+static inline __init bool count_can_be_sched_clock(void)
+{
+ if (IS_ENABLED(CONFIG_CPU_FREQ))
+ return false;
+
+ if (num_possible_cpus() > 1 &&
+ !IS_ENABLED(CONFIG_HAVE_UNSTABLE_SCHED_CLOCK))
+ return false;
+
+ return true;
+}
+
#ifdef CONFIG_CPU_FREQ
static bool __read_mostly r4k_clock_unstable;
@@ -125,9 +137,8 @@ int __init init_r4k_clocksource(void)
clocksource_register_hz(&clocksource_mips, mips_hpt_frequency);
-#ifndef CONFIG_CPU_FREQ
- sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency);
-#endif
+ if (count_can_be_sched_clock())
+ sched_clock_register(r4k_read_sched_clock, 32, mips_hpt_frequency);
return 0;
}
--
2.43.0
next prev parent reply other threads:[~2024-06-12 8:54 UTC|newest]
Thread overview: 17+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-06-12 8:54 [PATCH v2 0/7] MIPS: clocksource cumulative enhancements Jiaxun Yang
2024-06-12 8:54 ` [PATCH v2 1/7] MIPS: csrc-r4k: Refine rating computation Jiaxun Yang
2024-06-12 8:54 ` [PATCH v2 2/7] MIPS: csrc-r4k: Apply verification clocksource flags Jiaxun Yang
2024-08-06 4:09 ` Guenter Roeck
2024-08-06 5:06 ` Jiaxun Yang
2024-08-06 5:13 ` Guenter Roeck
2024-08-06 15:06 ` Guenter Roeck
2024-08-08 7:35 ` Jiaxun Yang
2024-06-12 8:54 ` [PATCH v2 3/7] MIPS: csrc-r4k: Select HAVE_UNSTABLE_SCHED_CLOCK if SMP && 64BIT Jiaxun Yang
2024-06-12 8:54 ` Jiaxun Yang [this message]
2024-06-12 8:54 ` [PATCH v2 5/7] MIPS: sync-r4k: Rework based on x86 tsc_sync Jiaxun Yang
2024-06-12 8:54 ` [PATCH v2 6/7] clocksource: mips-gic-timer: Refine rating computation Jiaxun Yang
2024-06-21 11:18 ` Jiaxun Yang
2024-06-12 8:54 ` [PATCH v2 7/7] clocksource: mips-gic-timer: Correct sched_clock width Jiaxun Yang
2024-07-03 5:59 ` [PATCH v2 0/7] MIPS: clocksource cumulative enhancements Jiaxun Yang
2024-07-03 15:24 ` Thomas Bogendoerfer
2024-07-08 16:40 ` Daniel Lezcano
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