From: Sergey Matsievskiy <matsievskiysv@gmail.com>
To: tglx@linutronix.de
Cc: maz@kernel.org, alexandre.belloni@bootlin.com,
gregory.clement@bootlin.com, lars.povlsen@microchip.com,
UNGLinuxDriver@microchip.com, linux-mips@vger.kernel.org,
linux-kernel@vger.kernel.org,
Sergey Matsievskiy <matsievskiysv@gmail.com>
Subject: [PATCH 2/2] irqchip/ocelot: Comment sticky register clearing code
Date: Wed, 25 Sep 2024 21:44:16 +0300 [thread overview]
Message-ID: <20240925184416.54204-3-matsievskiysv@gmail.com> (raw)
In-Reply-To: <20240925184416.54204-1-matsievskiysv@gmail.com>
Add comment to the sticky register clearing code.
Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
---
drivers/irqchip/irq-mscc-ocelot.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index c19ab379e8c5..3dc745b14caf 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -84,6 +84,12 @@ static void ocelot_irq_unmask(struct irq_data *data)
u32 val;
irq_gc_lock(gc);
+ /*
+ * Clear sticky bits for edge mode interrupts.
+ * Serval has only one trigger register replication, but the adjacent
+ * register is always read as zero, so there's no need to handle this
+ * case separately.
+ */
val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |
irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));
if (!(val & mask))
--
2.39.2
prev parent reply other threads:[~2024-09-25 18:44 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-25 18:44 [PATCH 0/2] irqchip/ocelot: Fix trigger register address Sergey Matsievskiy
2024-09-25 18:44 ` [PATCH 1/2] " Sergey Matsievskiy
2024-09-25 18:44 ` Sergey Matsievskiy [this message]
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