[PATCH 0/2] irqchip/ocelot: Fix trigger register address

[PATCH 0/2] irqchip/ocelot: Fix trigger register address

[Sergey Matsievskiy]

Use main interrupt trigger registers instead of device interrupt trigger
registers.

Controllers, supported by this driver, have two sets of registers:
* (main) interrupt registers control peripheral interrupt sources;
* device interrupt registers configure per-device (network interface)
interrupts and act as an extra stage before the main interrupt registers.

In the driver unmask code, device trigger registers are used in the mask
calculation of the main interrupt sticky register, mixing two kinds of
registers.
This mix up does not manifest itself because the current implementation
only uses level interrupts, but will be evident with addition of the edge
interrupts. The first patch fixes this mix up.

Second patch adds the comment to the sticky bit clearing code as it's not
immediately obvious why Serval family is not handled specially, even though
it has only one interrupt trigger register replication.

Interrupt controller behavior was tested on Jaguar2C VSC7448.

Sergey Matsievskiy (2):
  irqchip/ocelot: Fix trigger register address
  irqchip/ocelot: Comment sticky register clearing code

 drivers/irqchip/irq-mscc-ocelot.c | 10 ++++++++--
 1 file changed, 8 insertions(+), 2 deletions(-)

-- 
2.39.2

[PATCH 1/2] irqchip/ocelot: Fix trigger register address

[Sergey Matsievskiy]

Use main interrupt trigger registers instead of device interrupt trigger
registers.

Controllers, supported by this driver, have two sets of registers:
* (main) interrupt registers control peripheral interrupt sources;
* device interrupt registers configure per-device (network interface)
interrupts and act as an extra stage before the main interrupt registers.

In the driver unmask code, device trigger registers are used in the mask
calculation of the main interrupt sticky register, mixing two kinds of
registers. Use main interrupt trigger register instead.

Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
---
 drivers/irqchip/irq-mscc-ocelot.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index 4d0c3532dbe7..c19ab379e8c5 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -37,7 +37,7 @@ static struct chip_props ocelot_props = {
 	.reg_off_ena_clr	= 0x1c,
 	.reg_off_ena_set	= 0x20,
 	.reg_off_ident		= 0x38,
-	.reg_off_trigger	= 0x5c,
+	.reg_off_trigger	= 0x4,
 	.n_irq			= 24,
 };
 
@@ -70,7 +70,7 @@ static struct chip_props jaguar2_props = {
 	.reg_off_ena_clr	= 0x1c,
 	.reg_off_ena_set	= 0x20,
 	.reg_off_ident		= 0x38,
-	.reg_off_trigger	= 0x5c,
+	.reg_off_trigger	= 0x4,
 	.n_irq			= 29,
 };
 
-- 
2.39.2

[PATCH 2/2] irqchip/ocelot: Comment sticky register clearing code

[Sergey Matsievskiy]

Add comment to the sticky register clearing code.

Signed-off-by: Sergey Matsievskiy <matsievskiysv@gmail.com>
---
 drivers/irqchip/irq-mscc-ocelot.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/irqchip/irq-mscc-ocelot.c b/drivers/irqchip/irq-mscc-ocelot.c
index c19ab379e8c5..3dc745b14caf 100644
--- a/drivers/irqchip/irq-mscc-ocelot.c
+++ b/drivers/irqchip/irq-mscc-ocelot.c
@@ -84,6 +84,12 @@ static void ocelot_irq_unmask(struct irq_data *data)
 	u32 val;
 
 	irq_gc_lock(gc);
+	/*
+	 * Clear sticky bits for edge mode interrupts.
+	 * Serval has only one trigger register replication, but the adjacent
+	 * register is always read as zero, so there's no need to handle this
+	 * case separately.
+	 */
 	val = irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 0)) |
 		irq_reg_readl(gc, ICPU_CFG_INTR_INTR_TRIGGER(p, 1));
 	if (!(val & mask))
-- 
2.39.2