[PATCH 00/13] Usable clocks on Mobileye EyeQ5 & EyeQ6H

[PATCH 00/13] Usable clocks on Mobileye EyeQ5 & EyeQ6H

[Théo Lebrun]

Now that clk-eyeq is in the clk-next tree, we can add the small(-ish)
details required to make the platform work fully. The work is mostly
about updating devicetrees to rely on the system-controller nodes as
clock providers.

--

Things we do:

 - In EyeQ5 devicetrees, remove all fixed-factor clocks that are derived
   from clk-eyeq PLLs. We expose those directly from clk-eyeq (using
   match data info). This is simpler to reason about.

   [PATCH 02/13] dt-bindings: clock: eyeq: add Mobileye EyeQ5 core clocks
   [PATCH 03/13] dt-bindings: clock: eyeq: add Mobileye EyeQ5 peripheral clocks
   [PATCH 06/13] clk: fixed-factor: add clk_hw_register_fixed_factor_index() function
   [PATCH 08/13] clk: eyeq: add fixed factor clocks infrastructure
   [PATCH 09/13] clk: eyeq: add EyeQ5 fixed factor clocks
   [PATCH 12/13] MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks

 - EyeQ6H devicetrees used fixed-clocks and didn't have
   system-controllers defined. Remove all that and define our syscons.

   [PATCH 04/13] dt-bindings: clock: eyeq: add Mobileye EyeQ6H central clocks
   [PATCH 05/13] dt-bindings: clock: eyeq: add Mobileye EyeQ6H west clocks
   [PATCH 10/13] clk: eyeq: add EyeQ6H central fixed factor clocks
   [PATCH 11/13] clk: eyeq: add EyeQ6H west fixed factor clocks
   [PATCH 13/13] MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks

 - Our bindings used to say that some compatibles require a clock cell
   (those that expose multiple clocks) and others do not. Remove that
   subtlety and enforce a clock cell for everyone.

   The goal is to make it easier to add clocks to compatibles that
   previously exposed a single one. It happens for two compatibles in
   this patch series (EyeQ6H central and west).

   This is a "revert". I had been advised in the initial patch that the
   behavior was a bad idea. I 100% agree with those comments.

   [PATCH 01/13] dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
   [PATCH 07/13] clk: eyeq: require clock index with phandle in all cases

--

In which tree patches should go:

 - clk:
   [PATCH 02/13] dt-bindings: clock: eyeq: add Mobileye EyeQ5 core clocks
   [PATCH 03/13] dt-bindings: clock: eyeq: add Mobileye EyeQ5 peripheral clocks
   [PATCH 04/13] dt-bindings: clock: eyeq: add Mobileye EyeQ6H central clocks
   [PATCH 05/13] dt-bindings: clock: eyeq: add Mobileye EyeQ6H west clocks
   [PATCH 06/13] clk: fixed-factor: add clk_hw_register_fixed_factor_index() function
   [PATCH 07/13] clk: eyeq: require clock index with phandle in all cases
   [PATCH 08/13] clk: eyeq: add fixed factor clocks infrastructure
   [PATCH 09/13] clk: eyeq: add EyeQ5 fixed factor clocks
   [PATCH 10/13] clk: eyeq: add EyeQ6H central fixed factor clocks
   [PATCH 11/13] clk: eyeq: add EyeQ6H west fixed factor clocks

 - MIPS:
   [PATCH 01/13] dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
   [PATCH 12/13] MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks
   [PATCH 13/13] MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks

Reasoning: we need the clock indexes from dt-bindings headers to avoid
breaking the driver build, so patches 2-5 must go in clk-next.

Note about devicetree patches 12-13: other patches on the same
devicetrees are in the mailing-lists, with which I expect conflicts.
All should be straight-forward to resolve.

--

Question: I am a bit afraid about the process for clocks in the future.
Say we want to add I2C on EyeQ5 [0]. Steps will be:
 - The dt-bindings headers will get a new offset.
 - The clk-eyeq driver will get its private clocks indexes updated.
 - Then the clocks will be accessible from devicetree.

Those are somewhat unrelated to a series that is enabling I2C on a
platform. Should I expose the few clocks I already know we'll be
needing soon enough (I2C, SPI, EMMC)? The rest, I am unsure about the
structure and I'd prefer not exposing them.

Thanks,
Have a nice day,
Théo

[0]: https://lore.kernel.org/all/20241009-mbly-i2c-v3-0-e7fd13bcf1c4@bootlin.com/

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
Théo Lebrun (13):
      dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles
      dt-bindings: clock: eyeq: add Mobileye EyeQ5 core clocks
      dt-bindings: clock: eyeq: add Mobileye EyeQ5 peripheral clocks
      dt-bindings: clock: eyeq: add Mobileye EyeQ6H central clocks
      dt-bindings: clock: eyeq: add Mobileye EyeQ6H west clocks
      clk: fixed-factor: add clk_hw_register_fixed_factor_index() function
      clk: eyeq: require clock index with phandle in all cases
      clk: eyeq: add fixed factor clocks infrastructure
      clk: eyeq: add EyeQ5 fixed factor clocks
      clk: eyeq: add EyeQ6H central fixed factor clocks
      clk: eyeq: add EyeQ6H west fixed factor clocks
      MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks
      MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks

 .../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml  |  24 +-
 arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi      | 270 ---------------------
 arch/mips/boot/dts/mobileye/eyeq5.dtsi             |  30 ++-
 .../boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi     |  52 ----
 arch/mips/boot/dts/mobileye/eyeq6h.dtsi            |  73 +++++-
 drivers/clk/clk-eyeq.c                             | 204 ++++++++++++++--
 drivers/clk/clk-fixed-factor.c                     |  11 +
 include/dt-bindings/clock/mobileye,eyeq5-clk.h     |  17 ++
 include/linux/clk-provider.h                       |   3 +
 9 files changed, 307 insertions(+), 377 deletions(-)
---
base-commit: 11713909beb7debd3d466a6dc302a33d91298be0
change-id: 20241030-mbly-clk-a877f3793eb2

Best regards,
-- 
Théo Lebrun <theo.lebrun@bootlin.com>

[PATCH 01/13] dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles

[Théo Lebrun]

Some compatibles expose a single clock. For those, we used to let them
using `#clock-cells = <0>` (ie <&olb> reference rather than <&olb 0>).

Switch away from that: enforce a cell for all compatibles. This is more
straight forward, and avoids devicetree changes whenever a compatible
goes from exposing a single clock to multiple ones.

Side benefit: dt-bindings is simpler.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 .../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml  | 24 +---------------------
 1 file changed, 1 insertion(+), 23 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
index f7e606d45ebcfc46ffe076e23a2ed514bfff9b8f..6d11472ba5a704d5d20f43776e5867f507a39242 100644
--- a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
+++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
@@ -41,9 +41,7 @@ properties:
     enum: [ 1, 2 ]
 
   '#clock-cells':
-    description:
-      Cell is clock index. Optional if compatible has a single clock.
-    enum: [ 0, 1 ]
+    const: 1
 
   clocks:
     maxItems: 1
@@ -312,26 +310,6 @@ allOf:
       properties:
         '#reset-cells': false
 
-    # Compatibles exposing a single clock.
-  - if:
-      properties:
-        compatible:
-          contains:
-            enum:
-              - mobileye,eyeq6h-central-olb
-              - mobileye,eyeq6h-east-olb
-              - mobileye,eyeq6h-west-olb
-              - mobileye,eyeq6h-ddr0-olb
-              - mobileye,eyeq6h-ddr1-olb
-    then:
-      properties:
-        '#clock-cells':
-          const: 0
-    else:
-      properties:
-        '#clock-cells':
-          const: 1
-
     # Only EyeQ5 has pinctrl in OLB.
   - if:
       not:

-- 
2.47.0

[PATCH 02/13] dt-bindings: clock: eyeq: add Mobileye EyeQ5 core clocks

[Théo Lebrun]

Add #defines for Mobileye EyeQ5 core 0 thru 3 inclusive.
Internally, those derive from EQ5C_PLL_CPU.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 include/dt-bindings/clock/mobileye,eyeq5-clk.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
index b433c1772c28fae818b3a6ba428d1f89000f9206..359f7cceaadb368998db714344595f0449963536 100644
--- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
@@ -19,6 +19,12 @@
 
 #define EQ5C_DIV_OSPI	10
 
+/* EQ5C_PLL_CPU children */
+#define EQ5C_CPU_CORE0	11
+#define EQ5C_CPU_CORE1	12
+#define EQ5C_CPU_CORE2	13
+#define EQ5C_CPU_CORE3	14
+
 #define EQ6LC_PLL_DDR		0
 #define EQ6LC_PLL_CPU		1
 #define EQ6LC_PLL_PER		2

-- 
2.47.0

[PATCH 03/13] dt-bindings: clock: eyeq: add Mobileye EyeQ5 peripheral clocks

[Théo Lebrun]

Add #defines for Mobileye EyeQ5 slow-speed peripheral bus clock (OCC)
and UART clock. Internally, those derive from EQ5C_PLL_PER.

OCC is standard naming convention on this platform.
Its exact meaning is unknown.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 include/dt-bindings/clock/mobileye,eyeq5-clk.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
index 359f7cceaadb368998db714344595f0449963536..7d9e700b5e59573c45919865d9c68a9e8cf6a9eb 100644
--- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
@@ -25,6 +25,10 @@
 #define EQ5C_CPU_CORE2	13
 #define EQ5C_CPU_CORE3	14
 
+/* EQ5C_PLL_PER children */
+#define EQ5C_PER_OCC	15
+#define EQ5C_PER_UART	16
+
 #define EQ6LC_PLL_DDR		0
 #define EQ6LC_PLL_CPU		1
 #define EQ6LC_PLL_PER		2

-- 
2.47.0

[PATCH 04/13] dt-bindings: clock: eyeq: add Mobileye EyeQ6H central clocks

[Théo Lebrun]

Add clock indexes for EyeQ6H central OLB.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 include/dt-bindings/clock/mobileye,eyeq5-clk.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
index 7d9e700b5e59573c45919865d9c68a9e8cf6a9eb..2356bc52646df9cfeb93df8120eb8f0bf80d97e9 100644
--- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
@@ -34,6 +34,9 @@
 #define EQ6LC_PLL_PER		2
 #define EQ6LC_PLL_VDI		3
 
+#define EQ6HC_CENTRAL_PLL_CPU	0
+#define EQ6HC_CENTRAL_CPU_OCC	1
+
 #define EQ6HC_SOUTH_PLL_VDI		0
 #define EQ6HC_SOUTH_PLL_PCIE		1
 #define EQ6HC_SOUTH_PLL_PER		2

-- 
2.47.0

[PATCH 05/13] dt-bindings: clock: eyeq: add Mobileye EyeQ6H west clocks

[Théo Lebrun]

Add clock indexes for EyeQ6H west OLB. Internal hierarchy is:

    PLL_PER
    └── PER_OCC
        └── PER_UART

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 include/dt-bindings/clock/mobileye,eyeq5-clk.h | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
index 2356bc52646df9cfeb93df8120eb8f0bf80d97e9..8efdf0feae8e43e7b84ff9ca12b8b90c3116240d 100644
--- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
@@ -37,6 +37,10 @@
 #define EQ6HC_CENTRAL_PLL_CPU	0
 #define EQ6HC_CENTRAL_CPU_OCC	1
 
+#define EQ6HC_WEST_PLL_PER	0
+#define EQ6HC_WEST_PER_OCC	1
+#define EQ6HC_WEST_PER_UART	2
+
 #define EQ6HC_SOUTH_PLL_VDI		0
 #define EQ6HC_SOUTH_PLL_PCIE		1
 #define EQ6HC_SOUTH_PLL_PER		2

-- 
2.47.0

[PATCH 06/13] clk: fixed-factor: add clk_hw_register_fixed_factor_index() function

[Théo Lebrun]

Add non-devres version of clk_hw_register_fixed_factor(), with parent
targeted using its index.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 drivers/clk/clk-fixed-factor.c | 11 +++++++++++
 include/linux/clk-provider.h   |  3 +++
 2 files changed, 14 insertions(+)

diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index 8fba63fc70c554df0d646dba75c5d70d0b184319..e62ae8794d445f685156276d5135448f340fca3f 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -241,6 +241,17 @@ struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *
 }
 EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_with_accuracy_fwname);
 
+struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev,
+		const char *name, unsigned int index, unsigned long flags,
+		unsigned int mult, unsigned int div)
+{
+	const struct clk_parent_data pdata = { .index = index };
+
+	return __clk_hw_register_fixed_factor(dev, NULL, name, NULL, NULL, &pdata,
+					      flags, mult, div, 0, 0, false);
+}
+EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_index);
+
 struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
 		const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 75444e250a7875a4fa90c9dea7a90b198f6be2b8..99ae3ffb94bc5ce2b8493509cf3548b03209852b 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -1142,6 +1142,9 @@ struct clk_hw *clk_hw_register_fixed_factor_with_accuracy_fwname(struct device *
 		struct device_node *np, const char *name, const char *fw_name,
 		unsigned long flags, unsigned int mult, unsigned int div,
 		unsigned long acc);
+struct clk_hw *clk_hw_register_fixed_factor_index(struct device *dev,
+		const char *name, unsigned int index, unsigned long flags,
+		unsigned int mult, unsigned int div);
 void clk_hw_unregister_fixed_factor(struct clk_hw *hw);
 struct clk_hw *devm_clk_hw_register_fixed_factor(struct device *dev,
 		const char *name, const char *parent_name, unsigned long flags,

-- 
2.47.0

[PATCH 07/13] clk: eyeq: require clock index with phandle in all cases

[Théo Lebrun]

We used to let compatibles with a single clock exposed to not have
a cell. Switch away from that and enforce a cell in all cases.

This is done at the same time as some compatibles
(mobileye,eyeq6h-{central,west}-olb) go from one to more clocks
exposed. Let's do the same switch and avoid future devicetree
work if/when others follow.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 12 ++----------
 1 file changed, 2 insertions(+), 10 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 77f1afb020a0247b9d73b59a88845b21a0d83b5e..ed4dab303d9121cd8bf453448b4c86547ea9244c 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -367,11 +367,7 @@ static int eqc_probe(struct platform_device *pdev)
 
 	eqc_probe_init_divs(dev, data, base, cells);
 
-	/* When providing a single clock, require no cell. */
-	if (clk_count == 1)
-		return of_clk_add_hw_provider(np, of_clk_hw_simple_get, cells->hws[0]);
-	else
-		return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
+	return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
 }
 
 /* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */
@@ -637,11 +633,7 @@ static void __init eqc_early_init(struct device_node *np,
 		}
 	}
 
-	/* When providing a single clock, require no cell. */
-	if (clk_count == 1)
-		ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, cells->hws[0]);
-	else
-		ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
+	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
 	if (ret) {
 		pr_err("failed registering clk provider: %d\n", ret);
 		goto err;

-- 
2.47.0

[PATCH 08/13] clk: eyeq: add fixed factor clocks infrastructure

[Théo Lebrun]

Driver can currently host two types of clocks:
 - PLLs derived directly from the main crystal (taken using a fwhandle).
 - Divider clocks derived from those PLLs.

PLLs can be instantiated from of_clk_init() or platform device probe,
using two separate clock providers. Divider clocks are all instantiated
at platform device probe.

Add a third type of clocks: fixed factors. Those can be instantiated at
both stages. They can be parented to any clock from the driver. Early
match data and match data store the list of fixed factor clocks.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 81 +++++++++++++++++++++++++++++++++++++++++++++-----
 1 file changed, 73 insertions(+), 8 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index ed4dab303d9121cd8bf453448b4c86547ea9244c..dcd1d996255fc97449ac1bccb6a7c810d6e4c9db 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -2,11 +2,14 @@
 /*
  * PLL clock driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms.
  *
- * This controller handles read-only PLLs, all derived from the same main
- * crystal clock. It also exposes divider clocks, those are children to PLLs.
- * Parent clock is expected to be constant. This driver's registers live in
- * a shared region called OLB. Some PLLs are initialised early by of_clk_init();
- * if so, two clk providers are registered.
+ * This controller handles:
+ *  - Read-only PLLs, all derived from the same main crystal clock.
+ *  - It also exposes divider clocks, those are children to PLLs.
+ *  - Fixed factor clocks, children to PLLs.
+ *
+ * Parent clock is expected to be constant. This driver's registers live in a
+ * shared region called OLB. Some PLLs and fixed-factors are initialised early
+ * by of_clk_init(); if so, two clk providers are registered.
  *
  * We use eqc_ as prefix, as-in "EyeQ Clock", but way shorter.
  *
@@ -86,6 +89,14 @@ struct eqc_div {
 	u8		width;
 };
 
+struct eqc_fixed_factor {
+	unsigned int	index;
+	const char	*name;
+	unsigned int	mult;
+	unsigned int	div;
+	unsigned int	parent;
+};
+
 struct eqc_match_data {
 	unsigned int		pll_count;
 	const struct eqc_pll	*plls;
@@ -93,6 +104,9 @@ struct eqc_match_data {
 	unsigned int		div_count;
 	const struct eqc_div	*divs;
 
+	unsigned int			fixed_factor_count;
+	const struct eqc_fixed_factor	*fixed_factors;
+
 	const char		*reset_auxdev_name;
 	const char		*pinctrl_auxdev_name;
 
@@ -103,6 +117,9 @@ struct eqc_early_match_data {
 	unsigned int		early_pll_count;
 	const struct eqc_pll	*early_plls;
 
+	unsigned int			early_fixed_factor_count;
+	const struct eqc_fixed_factor	*early_fixed_factors;
+
 	/*
 	 * We want our of_xlate callback to EPROBE_DEFER instead of dev_err()
 	 * and EINVAL. For that, we must know the total clock count.
@@ -276,6 +293,35 @@ static void eqc_probe_init_divs(struct device *dev, const struct eqc_match_data
 	}
 }
 
+static void eqc_probe_init_fixed_factors(struct device *dev,
+					 const struct eqc_match_data *data,
+					 struct clk_hw_onecell_data *cells)
+{
+	const struct eqc_fixed_factor *ff;
+	struct clk_hw *hw, *parent_hw;
+	unsigned int i;
+
+	for (i = 0; i < data->fixed_factor_count; i++) {
+		ff = &data->fixed_factors[i];
+		parent_hw = cells->hws[ff->parent];
+
+		if (IS_ERR(parent_hw)) {
+			/* Parent is in early clk provider. */
+			hw = clk_hw_register_fixed_factor_index(dev, ff->name,
+					ff->parent, 0, ff->mult, ff->div);
+		} else {
+			/* Avoid clock lookup when we already have the hw reference. */
+			hw = clk_hw_register_fixed_factor_parent_hw(dev, ff->name,
+					parent_hw, 0, ff->mult, ff->div);
+		}
+
+		cells->hws[ff->index] = hw;
+		if (IS_ERR(hw))
+			dev_warn(dev, "failed registering %s: %pe\n",
+				 ff->name, hw);
+	}
+}
+
 static void eqc_auxdev_release(struct device *dev)
 {
 	struct auxiliary_device *adev = to_auxiliary_dev(dev);
@@ -349,10 +395,11 @@ static int eqc_probe(struct platform_device *pdev)
 				 KBUILD_MODNAME, data->pinctrl_auxdev_name, ret);
 	}
 
-	if (data->pll_count + data->div_count == 0)
+	if (data->pll_count + data->div_count + data->fixed_factor_count == 0)
 		return 0; /* Zero clocks, we are done. */
 
-	clk_count = data->pll_count + data->div_count + data->early_clk_count;
+	clk_count = data->pll_count + data->div_count +
+		    data->fixed_factor_count + data->early_clk_count;
 	cells = kzalloc(struct_size(cells, hws, clk_count), GFP_KERNEL);
 	if (!cells)
 		return -ENOMEM;
@@ -367,6 +414,8 @@ static int eqc_probe(struct platform_device *pdev)
 
 	eqc_probe_init_divs(dev, data, base, cells);
 
+	eqc_probe_init_fixed_factors(dev, data, cells);
+
 	return of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
 }
 
@@ -580,7 +629,8 @@ static void __init eqc_early_init(struct device_node *np,
 	void __iomem *base;
 	int ret;
 
-	clk_count = early_data->early_pll_count + early_data->late_clk_count;
+	clk_count = early_data->early_pll_count + early_data->early_fixed_factor_count +
+		    early_data->late_clk_count;
 	cells = kzalloc(struct_size(cells, hws, clk_count), GFP_KERNEL);
 	if (!cells) {
 		ret = -ENOMEM;
@@ -633,6 +683,21 @@ static void __init eqc_early_init(struct device_node *np,
 		}
 	}
 
+	for (i = 0; i < early_data->early_fixed_factor_count; i++) {
+		const struct eqc_fixed_factor *ff = &early_data->early_fixed_factors[i];
+		struct clk_hw *parent_hw = cells->hws[ff->parent];
+		struct clk_hw *hw;
+
+		hw = clk_hw_register_fixed_factor_parent_hw(NULL,
+				ff->name, parent_hw, 0, ff->mult, ff->div);
+		cells->hws[ff->index] = hw;
+		if (IS_ERR(hw)) {
+			pr_err("failed registering %s: %pe\n", ff->name, hw);
+			ret = PTR_ERR(hw);
+			goto err;
+		}
+	}
+
 	ret = of_clk_add_hw_provider(np, of_clk_hw_onecell_get, cells);
 	if (ret) {
 		pr_err("failed registering clk provider: %d\n", ret);

-- 
2.47.0

[PATCH 09/13] clk: eyeq: add EyeQ5 fixed factor clocks

[Théo Lebrun]

Expose additional clocks on EyeQ5. Some indexes come from dt-bindings
headers, others are private to the driver.

Few clocks are early (of_clk_init() stage: core clocks and UART clock),
others can wait until platform device probe. The source for this list
is downstream Mobileye kernel and some internal documentation.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 92 ++++++++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 90 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index dcd1d996255fc97449ac1bccb6a7c810d6e4c9db..6337736ef0ccb963fc16f66b1c78c33fdff0f99f 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -436,6 +436,86 @@ static const struct eqc_pll eqc_eyeq5_plls[] = {
 	{ .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg64 = 0x074 },
 };
 
+/* EQ5C_PLL_CPU children */
+#define EQ5C_CPU_OCC		17
+#define EQ5C_CPU_SI_CSS0	18
+#define EQ5C_CPU_CPC		19
+#define EQ5C_CPU_CM		20
+#define EQ5C_CPU_MEM		21
+#define EQ5C_CPU_OCC_ISRAM	22
+#define EQ5C_CPU_ISRAM		23
+#define EQ5C_CPU_OCC_DBU	24
+#define EQ5C_CPU_SI_DBU_TP	25
+
+/* EQ5C_PLL_VDI children */
+#define EQ5C_VDI_OCC_VDI	26
+#define EQ5C_VDI_VDI		27
+#define EQ5C_VDI_OCC_CAN_SER	28
+#define EQ5C_VDI_CAN_SER	29
+#define EQ5C_VDI_I2C_SER	30
+
+/* EQ5C_PLL_PER children */
+#define EQ5C_PER_PERIPH		31
+#define EQ5C_PER_CAN		32
+#define EQ5C_PER_SPI		33
+#define EQ5C_PER_I2C		34
+#define EQ5C_PER_TIMER		35
+#define EQ5C_PER_GPIO		36
+#define EQ5C_PER_EMMC		37
+#define EQ5C_PER_CCF		38
+#define EQ5C_PER_OCC_MJPEG	39
+#define EQ5C_PER_HSM		40
+#define EQ5C_PER_MJPEG		41
+#define EQ5C_PER_FCMU_A		42
+#define EQ5C_PER_OCC_PCI	43
+
+static const struct eqc_fixed_factor eqc_eyeq5_early_fixed_factors[] = {
+	/* EQ5C_PLL_CPU children */
+	{ EQ5C_CPU_OCC,		"occ-cpu",	1, 1,	EQ5C_PLL_CPU },
+	{ EQ5C_CPU_SI_CSS0,	"si-css0",	1, 1,	EQ5C_CPU_OCC },
+	{ EQ5C_CPU_CORE0,	"core0",	1, 1,	EQ5C_CPU_SI_CSS0 },
+	{ EQ5C_CPU_CORE1,	"core1",	1, 1,	EQ5C_CPU_SI_CSS0 },
+	{ EQ5C_CPU_CORE2,	"core2",	1, 1,	EQ5C_CPU_SI_CSS0 },
+	{ EQ5C_CPU_CORE3,	"core3",	1, 1,	EQ5C_CPU_SI_CSS0 },
+
+	/* EQ5C_PLL_PER children */
+	{ EQ5C_PER_OCC,		"occ-periph",	1, 16,	EQ5C_PLL_PER },
+	{ EQ5C_PER_UART,	"uart",		1, 1,	EQ5C_PER_OCC },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq5_fixed_factors[] = {
+	/* EQ5C_PLL_CPU children */
+	{ EQ5C_CPU_CPC,		"cpc",		1, 1,	EQ5C_CPU_SI_CSS0 },
+	{ EQ5C_CPU_CM,		"cm",		1, 1,	EQ5C_CPU_SI_CSS0 },
+	{ EQ5C_CPU_MEM,		"mem",		1, 1,	EQ5C_CPU_SI_CSS0 },
+	{ EQ5C_CPU_OCC_ISRAM,	"occ-isram",	1, 2,	EQ5C_PLL_CPU },
+	{ EQ5C_CPU_ISRAM,	"isram",	1, 1,	EQ5C_CPU_OCC_ISRAM },
+	{ EQ5C_CPU_OCC_DBU,	"occ-dbu",	1, 10,	EQ5C_PLL_CPU },
+	{ EQ5C_CPU_SI_DBU_TP,	"si-dbu-tp",	1, 1,	EQ5C_CPU_OCC_DBU },
+
+	/* EQ5C_PLL_VDI children */
+	{ EQ5C_VDI_OCC_VDI,	"occ-vdi",	1, 2,	EQ5C_PLL_VDI },
+	{ EQ5C_VDI_VDI,		"vdi",		1, 1,	EQ5C_VDI_OCC_VDI },
+	{ EQ5C_VDI_OCC_CAN_SER,	"occ-can-ser",	1, 16,	EQ5C_PLL_VDI },
+	{ EQ5C_VDI_CAN_SER,	"can-ser",	1, 1,	EQ5C_VDI_OCC_CAN_SER },
+	{ EQ5C_VDI_I2C_SER,	"i2c-ser",	1, 20,	EQ5C_PLL_VDI },
+
+	/* EQ5C_PLL_PER children */
+	{ EQ5C_PER_PERIPH,	"periph",	1, 1,	EQ5C_PER_OCC },
+	{ EQ5C_PER_CAN,		"can",		1, 1,	EQ5C_PER_OCC },
+	{ EQ5C_PER_SPI,		"spi",		1, 1,	EQ5C_PER_OCC },
+	{ EQ5C_PER_I2C,		"i2c",		1, 1,	EQ5C_PER_OCC },
+	{ EQ5C_PER_TIMER,	"timer",	1, 1,	EQ5C_PER_OCC },
+	{ EQ5C_PER_GPIO,	"gpio",		1, 1,	EQ5C_PER_OCC },
+	{ EQ5C_PER_EMMC,	"emmc-sys",	1, 10,	EQ5C_PLL_PER },
+	{ EQ5C_PER_CCF,		"ccf-ctrl",	1, 4,	EQ5C_PLL_PER },
+	{ EQ5C_PER_OCC_MJPEG,	"occ-mjpeg",	1, 2,	EQ5C_PLL_PER },
+	{ EQ5C_PER_HSM,		"hsm",		1, 1,	EQ5C_PER_OCC_MJPEG },
+	{ EQ5C_PER_MJPEG,	"mjpeg",	1, 1,	EQ5C_PER_OCC_MJPEG },
+	{ EQ5C_PER_FCMU_A,	"fcmu-a",	1, 20,	EQ5C_PLL_PER },
+	{ EQ5C_PER_OCC_PCI,	"occ-pci-sys",	1, 8,	EQ5C_PLL_PER },
+};
+
 static const struct eqc_div eqc_eyeq5_divs[] = {
 	{
 		.index = EQ5C_DIV_OSPI,
@@ -451,7 +531,11 @@ static const struct eqc_early_match_data eqc_eyeq5_early_match_data __initconst
 	.early_pll_count	= ARRAY_SIZE(eqc_eyeq5_early_plls),
 	.early_plls		= eqc_eyeq5_early_plls,
 
-	.late_clk_count		= ARRAY_SIZE(eqc_eyeq5_plls) + ARRAY_SIZE(eqc_eyeq5_divs),
+	.early_fixed_factor_count	= ARRAY_SIZE(eqc_eyeq5_early_fixed_factors),
+	.early_fixed_factors		= eqc_eyeq5_early_fixed_factors,
+
+	.late_clk_count		= ARRAY_SIZE(eqc_eyeq5_plls) + ARRAY_SIZE(eqc_eyeq5_divs) +
+				  ARRAY_SIZE(eqc_eyeq5_fixed_factors),
 };
 
 static const struct eqc_match_data eqc_eyeq5_match_data = {
@@ -461,10 +545,14 @@ static const struct eqc_match_data eqc_eyeq5_match_data = {
 	.div_count	= ARRAY_SIZE(eqc_eyeq5_divs),
 	.divs		= eqc_eyeq5_divs,
 
+	.fixed_factor_count	= ARRAY_SIZE(eqc_eyeq5_fixed_factors),
+	.fixed_factors		= eqc_eyeq5_fixed_factors,
+
 	.reset_auxdev_name = "reset",
 	.pinctrl_auxdev_name = "pinctrl",
 
-	.early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_plls),
+	.early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_plls) +
+			   ARRAY_SIZE(eqc_eyeq5_early_fixed_factors),
 };
 
 static const struct eqc_pll eqc_eyeq6l_plls[] = {

-- 
2.47.0

[PATCH 10/13] clk: eyeq: add EyeQ6H central fixed factor clocks

[Théo Lebrun]

Previous setup was:
 - pll-cpu clock registered from driver at of_clk_init();
 - occ-cpu clock registered from DT using fixed-factor-clock compatible.

Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use
that capability to register occ-cpu.

Also switch from hard-coded index 0 for pll-cpu to using the
EQ6HC_CENTRAL_PLL_CPU constant by exposed dt-bindings headers.

occ-cpu is exposed at of_clk_init() because it gets used by both the DT
CPU nodes and the GIC timer.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 6337736ef0ccb963fc16f66b1c78c33fdff0f99f..4f6aa852038cfc4db0fc4473cf5e50c6c254b9ee 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -691,12 +691,19 @@ builtin_platform_driver(eqc_driver);
 
 /* Required early for GIC timer. */
 static const struct eqc_pll eqc_eyeq6h_central_early_plls[] = {
-	{ .index = 0, .name = "pll-cpu", .reg64 = 0x02C },
+	{ .index = EQ6HC_CENTRAL_PLL_CPU, .name = "pll-cpu", .reg64 = 0x02C },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factors[] = {
+	{ EQ6HC_CENTRAL_CPU_OCC, "occ-cpu", 1, 1, EQ6HC_CENTRAL_PLL_CPU },
 };
 
 static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __initconst = {
 	.early_pll_count	= ARRAY_SIZE(eqc_eyeq6h_central_early_plls),
 	.early_plls		= eqc_eyeq6h_central_early_plls,
+
+	.early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6h_central_early_fixed_factors),
+	.early_fixed_factors = eqc_eyeq6h_central_early_fixed_factors,
 };
 
 /* Required early for UART. */

-- 
2.47.0

[PATCH 11/13] clk: eyeq: add EyeQ6H west fixed factor clocks

[Théo Lebrun]

Previous setup was:
 - pll-west clock registered from driver at of_clk_init();
 - Both OCC and UART clocks registered from DT using fixed-factor-clock
   compatible.

Now that drivers/clk/clk-eyeq.c supports registering fixed factors, use
that capability to register west-per-occ and west-per-uart (giving them
proper names at the same time).

Also switch from hard-coded index 0 for pll-west to using the
EQ6HC_WEST_PLL_PER constant by exposed dt-bindings headers.

All get exposed at of_clk_init() because they get used by the AMBA PL011
serial ports. Those are instantiated before platform bus infrastructure.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 4f6aa852038cfc4db0fc4473cf5e50c6c254b9ee..f3ef4293b97bd553fbfd74b8dac4811772729458 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -708,12 +708,20 @@ static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __i
 
 /* Required early for UART. */
 static const struct eqc_pll eqc_eyeq6h_west_early_plls[] = {
-	{ .index = 0, .name = "pll-west", .reg64 = 0x074 },
+	{ .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg64 = 0x074 },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[] = {
+	{ EQ6HC_WEST_PER_OCC,  "west-per-occ",  1, 10, EQ6HC_WEST_PLL_PER },
+	{ EQ6HC_WEST_PER_UART, "west-per-uart", 1, 1,  EQ6HC_WEST_PER_OCC },
 };
 
 static const struct eqc_early_match_data eqc_eyeq6h_west_early_match_data __initconst = {
 	.early_pll_count	= ARRAY_SIZE(eqc_eyeq6h_west_early_plls),
 	.early_plls		= eqc_eyeq6h_west_early_plls,
+
+	.early_fixed_factor_count = ARRAY_SIZE(eqc_eyeq6h_west_early_fixed_factors),
+	.early_fixed_factors = eqc_eyeq6h_west_early_fixed_factors,
 };
 
 static void __init eqc_early_init(struct device_node *np,

-- 
2.47.0

[PATCH 12/13] MIPS: mobileye: eyeq5: use OLB as provider for fixed factor clocks

[Théo Lebrun]

Change the structure of the clock tree: rather than individual
devicetree nodes registering each fixed factor clock derived from OLB
PLLs, have the OLB node provide the necessary clocks.

Remove eyeq5-clocks.dtsi and move the three remaining "fixed-clock"s to
the main eyeq5.dtsi file.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi | 270 --------------------------
 arch/mips/boot/dts/mobileye/eyeq5.dtsi        |  30 ++-
 2 files changed, 24 insertions(+), 276 deletions(-)

diff --git a/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi
deleted file mode 100644
index 17a342cc744e57dc1f21262abdbfa97d4e4d58f3..0000000000000000000000000000000000000000
--- a/arch/mips/boot/dts/mobileye/eyeq5-clocks.dtsi
+++ /dev/null
@@ -1,270 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Copyright 2023 Mobileye Vision Technologies Ltd.
- */
-
-#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
-
-/ {
-	/* Fixed clock */
-	xtal: xtal {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <30000000>;
-	};
-
-/* PLL_CPU derivatives */
-	occ_cpu: occ-cpu {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_CPU>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	si_css0_ref_clk: si-css0-ref-clk { /* gate ClkRstGen_si_css0_ref */
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_cpu>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	cpc_clk: cpc-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&si_css0_ref_clk>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	core0_clk: core0-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&si_css0_ref_clk>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	core1_clk: core1-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&si_css0_ref_clk>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	core2_clk: core2-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&si_css0_ref_clk>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	core3_clk: core3-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&si_css0_ref_clk>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	cm_clk: cm-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&si_css0_ref_clk>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	mem_clk: mem-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&si_css0_ref_clk>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	occ_isram: occ-isram {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_CPU>;
-		#clock-cells = <0>;
-		clock-div = <2>;
-		clock-mult = <1>;
-	};
-	isram_clk: isram-clk { /* gate ClkRstGen_isram */
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_isram>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	occ_dbu: occ-dbu {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_CPU>;
-		#clock-cells = <0>;
-		clock-div = <10>;
-		clock-mult = <1>;
-	};
-	si_dbu_tp_pclk: si-dbu-tp-pclk { /* gate ClkRstGen_dbu */
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_dbu>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-/* PLL_VDI derivatives */
-	occ_vdi: occ-vdi {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_VDI>;
-		#clock-cells = <0>;
-		clock-div = <2>;
-		clock-mult = <1>;
-	};
-	vdi_clk: vdi-clk { /* gate ClkRstGen_vdi */
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_vdi>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	occ_can_ser: occ-can-ser {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_VDI>;
-		#clock-cells = <0>;
-		clock-div = <16>;
-		clock-mult = <1>;
-	};
-	can_ser_clk: can-ser-clk { /* gate ClkRstGen_can_ser */
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_can_ser>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	i2c_ser_clk: i2c-ser-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_VDI>;
-		#clock-cells = <0>;
-		clock-div = <20>;
-		clock-mult = <1>;
-	};
-/* PLL_PER derivatives */
-	occ_periph: occ-periph {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_PER>;
-		#clock-cells = <0>;
-		clock-div = <16>;
-		clock-mult = <1>;
-	};
-	periph_clk: periph-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_periph>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	can_clk: can-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_periph>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	spi_clk: spi-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_periph>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	uart_clk: uart-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_periph>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-	i2c_clk: i2c-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_periph>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-		clock-output-names = "i2c_clk";
-	};
-	timer_clk: timer-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_periph>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-		clock-output-names = "timer_clk";
-	};
-	gpio_clk: gpio-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_periph>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-		clock-output-names = "gpio_clk";
-	};
-	emmc_sys_clk: emmc-sys-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_PER>;
-		#clock-cells = <0>;
-		clock-div = <10>;
-		clock-mult = <1>;
-		clock-output-names = "emmc_sys_clk";
-	};
-	ccf_ctrl_clk: ccf-ctrl-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_PER>;
-		#clock-cells = <0>;
-		clock-div = <4>;
-		clock-mult = <1>;
-		clock-output-names = "ccf_ctrl_clk";
-	};
-	occ_mjpeg_core: occ-mjpeg-core {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_PER>;
-		#clock-cells = <0>;
-		clock-div = <2>;
-		clock-mult = <1>;
-		clock-output-names = "occ_mjpeg_core";
-	};
-	hsm_clk: hsm-clk { /* gate ClkRstGen_hsm */
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_mjpeg_core>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-		clock-output-names = "hsm_clk";
-	};
-	mjpeg_core_clk: mjpeg-core-clk { /* gate ClkRstGen_mjpeg_gen */
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_mjpeg_core>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-		clock-output-names = "mjpeg_core_clk";
-	};
-	fcmu_a_clk: fcmu-a-clk {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_PER>;
-		#clock-cells = <0>;
-		clock-div = <20>;
-		clock-mult = <1>;
-		clock-output-names = "fcmu_a_clk";
-	};
-	occ_pci_sys: occ-pci-sys {
-		compatible = "fixed-factor-clock";
-		clocks = <&olb EQ5C_PLL_PER>;
-		#clock-cells = <0>;
-		clock-div = <8>;
-		clock-mult = <1>;
-		clock-output-names = "occ_pci_sys";
-	};
-	pclk: pclk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <250000000>;  /* 250MHz */
-	};
-	tsu_clk: tsu-clk {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <125000000>;  /* 125MHz */
-	};
-};
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index 0708771c193d064fa56be2c7f6115672b5c24d8d..5d73e8320b8efc1b4f68923482bf188c4345f1cb 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -5,7 +5,7 @@
 
 #include <dt-bindings/interrupt-controller/mips-gic.h>
 
-#include "eyeq5-clocks.dtsi"
+#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
 
 / {
 	#address-cells = <2>;
@@ -17,7 +17,7 @@ cpu@0 {
 			device_type = "cpu";
 			compatible = "img,i6500";
 			reg = <0>;
-			clocks = <&core0_clk>;
+			clocks = <&olb EQ5C_CPU_CORE0>;
 		};
 	};
 
@@ -64,6 +64,24 @@ cpu_intc: interrupt-controller {
 		#interrupt-cells = <1>;
 	};
 
+	xtal: xtal {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <30000000>;
+	};
+
+	pclk: pclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <250000000>;  /* 250MHz */
+	};
+
+	tsu_clk: tsu-clk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <125000000>;  /* 125MHz */
+	};
+
 	soc: soc {
 		#address-cells = <2>;
 		#size-cells = <2>;
@@ -76,7 +94,7 @@ uart0: serial@800000 {
 			reg-io-width = <4>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
-			clocks  = <&uart_clk>, <&occ_periph>;
+			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
 			clock-names = "uartclk", "apb_pclk";
 			resets = <&olb 0 10>;
 			pinctrl-names = "default";
@@ -89,7 +107,7 @@ uart1: serial@900000 {
 			reg-io-width = <4>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
-			clocks  = <&uart_clk>, <&occ_periph>;
+			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
 			clock-names = "uartclk", "apb_pclk";
 			resets = <&olb 0 11>;
 			pinctrl-names = "default";
@@ -102,7 +120,7 @@ uart2: serial@a00000 {
 			reg-io-width = <4>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
-			clocks  = <&uart_clk>, <&occ_periph>;
+			clocks  = <&olb EQ5C_PER_UART>, <&olb EQ5C_PER_OCC>;
 			clock-names = "uartclk", "apb_pclk";
 			resets = <&olb 0 12>;
 			pinctrl-names = "default";
@@ -135,7 +153,7 @@ gic: interrupt-controller@140000 {
 			timer {
 				compatible = "mti,gic-timer";
 				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-				clocks = <&core0_clk>;
+				clocks = <&olb EQ5C_CPU_CORE0>;
 			};
 		};
 	};

-- 
2.47.0

[PATCH 13/13] MIPS: mobileye: eyeq6h: add OLB nodes OLB and remove fixed clocks

[Théo Lebrun]

Change the declaration of clocks: remove all fixed clocks and declare
system-controllers (OLB) as clock providers.

Remove eyeq6h-fixed-clocks.dtsi and move the crystal clock to the main
eyeq6h.dtsi file.

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
 .../boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi     | 52 ---------------
 arch/mips/boot/dts/mobileye/eyeq6h.dtsi            | 73 ++++++++++++++++++++--
 2 files changed, 69 insertions(+), 56 deletions(-)

diff --git a/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi
deleted file mode 100644
index 5fa99e06fde7e8f4942aafe5f6064e2c6f7d83fd..0000000000000000000000000000000000000000
--- a/arch/mips/boot/dts/mobileye/eyeq6h-fixed-clocks.dtsi
+++ /dev/null
@@ -1,52 +0,0 @@
-// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
-/*
- * Copyright 2023 Mobileye Vision Technologies Ltd.
- */
-
-#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
-
-/ {
-	xtal: clock-30000000 {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <30000000>;
-	};
-
-	pll_west: clock-2000000000-west {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <2000000000>;
-	};
-
-	pll_cpu: clock-2000000000-cpu {
-		compatible = "fixed-clock";
-		#clock-cells = <0>;
-		clock-frequency = <2000000000>;
-	};
-
-	/* pll-cpu derivatives */
-	occ_cpu: clock-2000000000-occ-cpu {
-		compatible = "fixed-factor-clock";
-		clocks = <&pll_cpu>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-
-	/* pll-west derivatives */
-	occ_periph_w: clock-200000000 {
-		compatible = "fixed-factor-clock";
-		clocks = <&pll_west>;
-		#clock-cells = <0>;
-		clock-div = <10>;
-		clock-mult = <1>;
-	};
-	uart_clk: clock-200000000-uart {
-		compatible = "fixed-factor-clock";
-		clocks = <&occ_periph_w>;
-		#clock-cells = <0>;
-		clock-div = <1>;
-		clock-mult = <1>;
-	};
-
-};
diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
index 1db3c3cda2e395025075387bcb66ea0737fd37f6..4a1a43f351d39625b520a16d035cacd2e29d157c 100644
--- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
@@ -5,7 +5,7 @@
 
 #include <dt-bindings/interrupt-controller/mips-gic.h>
 
-#include "eyeq6h-fixed-clocks.dtsi"
+#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
 
 / {
 	#address-cells = <2>;
@@ -17,7 +17,7 @@ cpu@0 {
 			device_type = "cpu";
 			compatible = "img,i6500";
 			reg = <0>;
-			clocks = <&occ_cpu>;
+			clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
 		};
 	};
 
@@ -32,19 +32,42 @@ cpu_intc: interrupt-controller {
 		#interrupt-cells = <1>;
 	};
 
+	xtal: clock-30000000 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <30000000>;
+	};
+
 	soc: soc {
 		compatible = "simple-bus";
 		#address-cells = <2>;
 		#size-cells = <2>;
 		ranges;
 
+		olb_acc: system-controller@d2003000 {
+			compatible = "mobileye,eyeq6h-acc-olb", "syscon";
+			reg = <0x0 0xd2003000 0x0 0x1000>;
+			#reset-cells = <1>;
+			#clock-cells = <1>;
+			clocks = <&xtal>;
+			clock-names = "ref";
+		};
+
+		olb_central: system-controller@d3100000 {
+			compatible = "mobileye,eyeq6h-central-olb", "syscon";
+			reg = <0x0 0xd3100000 0x0 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&xtal>;
+			clock-names = "ref";
+		};
+
 		uart0: serial@d3331000 {
 			compatible = "arm,pl011", "arm,primecell";
 			reg = <0 0xd3331000 0x0 0x1000>;
 			reg-io-width = <4>;
 			interrupt-parent = <&gic>;
 			interrupts = <GIC_SHARED 43 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&occ_periph_w>, <&occ_periph_w>;
+			clocks = <&olb_west EQ6HC_WEST_PER_UART>, <&olb_west EQ6HC_WEST_PER_OCC>;
 			clock-names = "uartclk", "apb_pclk";
 		};
 
@@ -56,6 +79,15 @@ pinctrl_west: pinctrl@d3337000 {
 			pinctrl-single,function-mask = <0xffff>;
 		};
 
+		olb_west: system-controller@d3338000 {
+			compatible = "mobileye,eyeq6h-west-olb", "syscon";
+			reg = <0x0 0xd3338000 0x0 0x1000>;
+			#reset-cells = <1>;
+			#clock-cells = <1>;
+			clocks = <&xtal>;
+			clock-names = "ref";
+		};
+
 		pinctrl_east: pinctrl@d3357000 {
 			compatible = "pinctrl-single";
 			reg = <0x0 0xd3357000 0x0 0xb0>;
@@ -64,6 +96,23 @@ pinctrl_east: pinctrl@d3357000 {
 			pinctrl-single,function-mask = <0xffff>;
 		};
 
+		olb_east: system-controller@d3358000 {
+			compatible = "mobileye,eyeq6h-east-olb", "syscon";
+			reg = <0x0 0xd3358000 0x0 0x1000>;
+			#reset-cells = <1>;
+			#clock-cells = <1>;
+			clocks = <&xtal>;
+			clock-names = "ref";
+		};
+
+		olb_south: system-controller@d8013000 {
+			compatible = "mobileye,eyeq6h-south-olb", "syscon";
+			reg = <0x0 0xd8013000 0x0 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&xtal>;
+			clock-names = "ref";
+		};
+
 		pinctrl_south: pinctrl@d8014000 {
 			compatible = "pinctrl-single";
 			reg = <0x0 0xd8014000 0x0 0xf8>;
@@ -72,6 +121,22 @@ pinctrl_south: pinctrl@d8014000 {
 			pinctrl-single,function-mask = <0xffff>;
 		};
 
+		olb_ddr0: system-controller@e4080000 {
+			compatible = "mobileye,eyeq6h-ddr0-olb", "syscon";
+			reg = <0x0 0xe4080000 0x0 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&xtal>;
+			clock-names = "ref";
+		};
+
+		olb_ddr1: system-controller@e4081000 {
+			compatible = "mobileye,eyeq6h-ddr1-olb", "syscon";
+			reg = <0x0 0xe4081000 0x0 0x1000>;
+			#clock-cells = <1>;
+			clocks = <&xtal>;
+			clock-names = "ref";
+		};
+
 		gic: interrupt-controller@f0920000 {
 			compatible = "mti,gic";
 			reg = <0x0 0xf0920000 0x0 0x20000>;
@@ -89,7 +154,7 @@ gic: interrupt-controller@f0920000 {
 			timer {
 				compatible = "mti,gic-timer";
 				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
-				clocks = <&occ_cpu>;
+				clocks = <&olb_central EQ6HC_CENTRAL_CPU_OCC>;
 			};
 		};
 	};

-- 
2.47.0

Re: [PATCH 04/13] dt-bindings: clock: eyeq: add Mobileye EyeQ6H central clocks

[Krzysztof Kozlowski]

On Thu, Oct 31, 2024 at 04:52:54PM +0100, Théo Lebrun wrote:
> Add clock indexes for EyeQ6H central OLB.
> 
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
>  include/dt-bindings/clock/mobileye,eyeq5-clk.h | 3 +++
>  1 file changed, 3 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> index 7d9e700b5e59573c45919865d9c68a9e8cf6a9eb..2356bc52646df9cfeb93df8120eb8f0bf80d97e9 100644
> --- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> @@ -34,6 +34,9 @@
>  #define EQ6LC_PLL_PER		2
>  #define EQ6LC_PLL_VDI		3
>  
> +#define EQ6HC_CENTRAL_PLL_CPU	0
> +#define EQ6HC_CENTRAL_CPU_OCC	1
> +

Don't add define after define in separate patches. Logical change is to
add all defines at once, so multiple patches here should be squashed.

Best regards,
Krzysztof

Re: [PATCH 01/13] dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles

[Rob Herring]

On Thu, Oct 31, 2024 at 04:52:51PM +0100, Théo Lebrun wrote:
> Some compatibles expose a single clock. For those, we used to let them
> using `#clock-cells = <0>` (ie <&olb> reference rather than <&olb 0>).
> 
> Switch away from that: enforce a cell for all compatibles. This is more
> straight forward, and avoids devicetree changes whenever a compatible
> goes from exposing a single clock to multiple ones.

Your reasoning is flawed. Changing #clock-cells is an ABI break. So you 
should only be changing this if it was just wrong. And if it's not wrong 
in some cases, you shouldn't be changing those. The h/w either has 1 
clock or multiple and #clocks-cells should match.

> 
> Side benefit: dt-bindings is simpler.
> 
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> ---
>  .../bindings/soc/mobileye/mobileye,eyeq5-olb.yaml  | 24 +---------------------
>  1 file changed, 1 insertion(+), 23 deletions(-)
> 
> diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
> index f7e606d45ebcfc46ffe076e23a2ed514bfff9b8f..6d11472ba5a704d5d20f43776e5867f507a39242 100644
> --- a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
> +++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
> @@ -41,9 +41,7 @@ properties:
>      enum: [ 1, 2 ]
>  
>    '#clock-cells':
> -    description:
> -      Cell is clock index. Optional if compatible has a single clock.
> -    enum: [ 0, 1 ]
> +    const: 1
>  
>    clocks:
>      maxItems: 1
> @@ -312,26 +310,6 @@ allOf:
>        properties:
>          '#reset-cells': false
>  
> -    # Compatibles exposing a single clock.
> -  - if:
> -      properties:
> -        compatible:
> -          contains:
> -            enum:
> -              - mobileye,eyeq6h-central-olb
> -              - mobileye,eyeq6h-east-olb
> -              - mobileye,eyeq6h-west-olb
> -              - mobileye,eyeq6h-ddr0-olb
> -              - mobileye,eyeq6h-ddr1-olb
> -    then:
> -      properties:
> -        '#clock-cells':
> -          const: 0
> -    else:
> -      properties:
> -        '#clock-cells':
> -          const: 1
> -
>      # Only EyeQ5 has pinctrl in OLB.
>    - if:
>        not:
> 
> -- 
> 2.47.0
> 

Re: [PATCH 04/13] dt-bindings: clock: eyeq: add Mobileye EyeQ6H central clocks

[Théo Lebrun]

On Fri Nov 1, 2024 at 8:48 AM CET, Krzysztof Kozlowski wrote:
> On Thu, Oct 31, 2024 at 04:52:54PM +0100, Théo Lebrun wrote:
> > Add clock indexes for EyeQ6H central OLB.
> > 
> > Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
> > ---
> >  include/dt-bindings/clock/mobileye,eyeq5-clk.h | 3 +++
> >  1 file changed, 3 insertions(+)
> > 
> > diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> > index 7d9e700b5e59573c45919865d9c68a9e8cf6a9eb..2356bc52646df9cfeb93df8120eb8f0bf80d97e9 100644
> > --- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> > +++ b/include/dt-bindings/clock/mobileye,eyeq5-clk.h
> > @@ -34,6 +34,9 @@
> >  #define EQ6LC_PLL_PER		2
> >  #define EQ6LC_PLL_VDI		3
> >  
> > +#define EQ6HC_CENTRAL_PLL_CPU	0
> > +#define EQ6HC_CENTRAL_CPU_OCC	1
> > +
>
> Don't add define after define in separate patches. Logical change is to
> add all defines at once, so multiple patches here should be squashed.

Sure, I was not sure so I leaned in the safe bet direction. Squashing is
much easier than splitting. Also improved the commit message, which
will look like this for next revision (incoming soon):

--

dt-bindings: clock: eyeq: add more Mobileye EyeQ5/EyeQ6H clocks

Add #defines for Mobileye clock controller:

 - EyeQ5 core 0 thru 3 clocks. Internally:

      EQ5C_PLL_CPU:           already exposed
      └── EQ5C_CPU_OCC:       unexposed, no reason to do so
          ├── EQ5C_CPU_CORE0: new!
          ├── EQ5C_CPU_CORE1: new!
          ├── EQ5C_CPU_CORE2: new!
          └── EQ5C_CPU_CORE3: new!

 - EyeQ5 peripheral clocks. Internally:

      EQ5C_PLL_PER:          already exposed
      └── EQ5C_PER_OCC:      new!
          └── EQ5C_PER_UART: new!

 - EyeQ6H central OLB. Internally:

      EQ6HC_CENTRAL_PLL_CPU:     new!
      └── EQ6HC_CENTRAL_CPU_OCC: new!

 - EyeQ6H west OLB. Internally:

      EQ6HC_WEST_PLL_PER:          new!
      └── EQ6HC_WEST_PER_OCC:      new!
          └── EQ6HC_WEST_PER_UART: new!

Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>

--

Thanks Krzysztof,

--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH 01/13] dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles

[Théo Lebrun]

On Mon Nov 4, 2024 at 4:37 PM CET, Rob Herring wrote:
> On Thu, Oct 31, 2024 at 04:52:51PM +0100, Théo Lebrun wrote:
> > Some compatibles expose a single clock. For those, we used to let them
> > using `#clock-cells = <0>` (ie <&olb> reference rather than <&olb 0>).
> > 
> > Switch away from that: enforce a cell for all compatibles. This is more
> > straight forward, and avoids devicetree changes whenever a compatible
> > goes from exposing a single clock to multiple ones.
>
> Your reasoning is flawed. Changing #clock-cells is an ABI break. So you 
> should only be changing this if it was just wrong. And if it's not wrong 
> in some cases, you shouldn't be changing those. The h/w either has 1 
> clock or multiple and #clocks-cells should match.

I see your reasoning, and I agree that changing #clock-cells is an ABI
break. However, there are two things to take into account:

 - We do not (yet?) have an omniscient view of the hardware. We do not
   know what every single register in those memory regions do.

   Some clocks might be lurking in the shadows, especially as we don't
   support many HW capabilities yet.

 - The earlier the better. If we discover later down the road that,
   indeed, some more clocks were hiding, we'll have to do an ABI break.

   At that point, some people might actually be using the platform.
   Seeing what we currently have supported upstream versus the amount
   of HW blocks available in the SoC, I cannot imagine anyone using the
   platform with an upstream kernel.

So the choice is:
 - potential ABI break in the future, once people use the platform, or,
 - guaranteed ABI break now, when no one is using it.

I pick option two! Do you agree with the thought process?

Thanks Rob,

--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH 01/13] dt-bindings: soc: mobileye: set `#clock-cells = <1>` for all compatibles

[Rob Herring]

On Mon, Nov 04, 2024 at 05:46:10PM +0100, Théo Lebrun wrote:
> On Mon Nov 4, 2024 at 4:37 PM CET, Rob Herring wrote:
> > On Thu, Oct 31, 2024 at 04:52:51PM +0100, Théo Lebrun wrote:
> > > Some compatibles expose a single clock. For those, we used to let them
> > > using `#clock-cells = <0>` (ie <&olb> reference rather than <&olb 0>).
> > > 
> > > Switch away from that: enforce a cell for all compatibles. This is more
> > > straight forward, and avoids devicetree changes whenever a compatible
> > > goes from exposing a single clock to multiple ones.
> >
> > Your reasoning is flawed. Changing #clock-cells is an ABI break. So you 
> > should only be changing this if it was just wrong. And if it's not wrong 
> > in some cases, you shouldn't be changing those. The h/w either has 1 
> > clock or multiple and #clocks-cells should match.
> 
> I see your reasoning, and I agree that changing #clock-cells is an ABI
> break. However, there are two things to take into account:
> 
>  - We do not (yet?) have an omniscient view of the hardware. We do not
>    know what every single register in those memory regions do.
> 
>    Some clocks might be lurking in the shadows, especially as we don't
>    support many HW capabilities yet.
> 
>  - The earlier the better. If we discover later down the road that,
>    indeed, some more clocks were hiding, we'll have to do an ABI break.
> 
>    At that point, some people might actually be using the platform.
>    Seeing what we currently have supported upstream versus the amount
>    of HW blocks available in the SoC, I cannot imagine anyone using the
>    platform with an upstream kernel.
> 
> So the choice is:
>  - potential ABI break in the future, once people use the platform, or,
>  - guaranteed ABI break now, when no one is using it.
> 
> I pick option two! Do you agree with the thought process?

Ultimately, it is up to you and the maintainers for the platform to 
decide. I only ask that ABI breaks are called out as ABI breaks with 
reasoning given for the ABI break.

I had no clue whether you have access to RTL or are reverse engineering 
this or something in between.

Please summarize the above explanation for the commit msg.

Rob