[PATCH 00/19] Add clock and reset support for Mobileye eyeQ7H

[PATCH 00/19] Add clock and reset support for Mobileye eyeQ7H

[Benoît Monin]

This patchset brings the support of the OLB found in the new Mobileye SoC,
the eyeQ7H. Those Other Logic Blocks provide clock and reset functions
to the controllers of the chip. This series also contains changes to the
clock driver and its device tree binding to better match the hardware
found in the eyeQ chips.

In details, patches 1 and 2 rename the dt-binding yaml and header to
eyeq-olb.yaml and eyeq-clk.h. We drop the "5" from the filename since
the binding also applies to other eyeQ SoC (eyeQ6L, eyeQ6H and eyeQ7H).

Patches 3 and 4 add the compatibles entries and the clock indexes to
the dt-binding for the eyeQ7H.

Patch 5 introduces a dt-binding header for the reset indexes of the
eyeQ7H, similar to the header of the clock indexes.

Patch 6 adds the compatible entries to the reset-eyeq driver, and the
needed changes for the reset domain found in the eyeQ7H.

Patch 7 adds clk_hw_register_fixed_factor_with_accuracy to
clk-fixed-factor.c. This function allows registering a fixed factor with
both a parent clock and a known accuracy. This will be used to register
clocks referring to a parent clock registered in early init.

Patch 8 and 9 add validity checks to clk-divider.c. The first ensure that
the divider is even if the flag CLK_DIVIDER_EVEN_INTEGERS is set. The
second rejects the registration of clock with both a table and a flag set
if the flag leads to the table being ignored when computing the divider.

Patch 10 removes the post-divisor in the computation of the PLL frequency
in clk-eyeq.c. This change reflects how the clock signal is routed in
the OLB of all eyeQ SoC.

Patch 11 and 12 allow referencing to a parent clock by name for divider
and fixed fixed factor in clk-eyeq.c. This is needed by the eyeQ5 to
refer to clock registered in early init during probe.

Patch 13 to 15 prepare the introduction of new PLL types present in
the eyeQ7H OLB, by prefixing the PLL defines with the PLL type found in
eyeQ5 and eyeQ6 OLB, renaming the reg64 field and adding a type field
in eqc_pll.

Patch 16 adds the two PLL types found in the eyeQ7H to the clk-eyeq
driver.

Patch 17 adds a parent_name field to the eqc_pll structure. This will
be used to refer to other parent clock for the PLL found in the OLB of
the eyeQ7H.

Patch 18 adds an optional clk_div_table to divider in the clk-eyeq driver.

Finally, patch 19 declares all the compatible entries for the OLB of the
eyeQ7H in the clk-eyeq driver, making use of the changes introduced in
the previous patches.

To: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
To: Gregory CLEMENT <gregory.clement@bootlin.com>
To: Théo Lebrun <theo.lebrun@bootlin.com>
To: Rob Herring <robh@kernel.org>
To: Krzysztof Kozlowski <krzk+dt@kernel.org>
To: Conor Dooley <conor+dt@kernel.org>
To: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
To: Michael Turquette <mturquette@baylibre.com>
To: Stephen Boyd <sboyd@kernel.org>
To: Philipp Zabel <p.zabel@pengutronix.de>
Cc: Thomas Petazzoni <thomas.petazzoni@bootlin.com>
Cc: Tawfik Bayouk <tawfik.bayouk@mobileye.com>
Cc: Sari Khoury <sari.khoury@mobileye.com>
Cc: linux-mips@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-clk@vger.kernel.org

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
Benoît Monin (19):
      dt-bindings: soc: mobileye: rename to eyeq-olb.yaml
      dt-bindings: clock: mobileye: rename to eyeq-clk.h
      dt-bindings: soc: mobileye: add eyeQ7H compatibles
      dt-bindings: clock: mobileye: add eyeQ7H clock indexes
      dt-bindings: reset: add Mobileye eyeQ
      reset: eyeq: add eyeQ7H compatibles
      clk: fixed-factor: add clk_hw_register_fixed_factor_with_accuracy
      clk: divider: check divider validity for CLK_DIVIDER_EVEN_INTEGERS
      clk: divider: check validity of flags when a table is provided
      clk: eyeq: skip post-divisor when computing pll divisor
      clk: eyeq: rename the parent field to parent_idx
      clk: eyeq: lookup parent clock by name
      clk: eyeq: prefix the PLL registers with the PLL type
      clk: eyeq: rename the reg64 field of eqc_pll
      clk: eyeq: add a type for the PLL
      clk: eyeq: add two PLL types
      clk: eyeq: add a parent field to the pll
      clk: eyeq: add an optional clk_div_table to divider
      clk: eyeq: add eyeQ7H compatibles

 ...ileye,eyeq5-olb.yaml => mobileye,eyeq-olb.yaml} | 137 +++-
 MAINTAINERS                                        |   3 +-
 arch/mips/boot/dts/mobileye/eyeq5.dtsi             |   2 +-
 arch/mips/boot/dts/mobileye/eyeq6h.dtsi            |   2 +-
 drivers/clk/clk-divider.c                          |   9 +
 drivers/clk/clk-eyeq.c                             | 876 ++++++++++++++++++---
 drivers/clk/clk-fixed-factor.c                     |  12 +
 drivers/reset/reset-eyeq.c                         | 248 +++++-
 include/dt-bindings/clock/mobileye,eyeq-clk.h      | 175 ++++
 include/dt-bindings/clock/mobileye,eyeq5-clk.h     |  65 --
 include/dt-bindings/reset/mobileye,eyeq-reset.h    |  75 ++
 include/linux/clk-provider.h                       |   3 +
 12 files changed, 1414 insertions(+), 193 deletions(-)
---
base-commit: b320789d6883cc00ac78ce83bccbfe7ed58afcf0
change-id: 20250807-clk-eyeq7-f9c6ea43d138

Best regards,
-- 
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[PATCH 01/19] dt-bindings: soc: mobileye: rename to eyeq-olb.yaml

[Benoît Monin]

Drop the 5 from the binding name as the OLB described in it are found
in multiple Mobileye eyeQ SoCs.

The binding already contains entries for eyeQ6L and eyeQ6H OLBs
alongside the one for the eyeQ5.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 .../soc/mobileye/{mobileye,eyeq5-olb.yaml => mobileye,eyeq-olb.yaml}    | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.yaml
similarity index 99%
rename from Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
rename to Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.yaml
index 6d11472ba5a704d5d20f43776e5867f507a39242..a1fb33ab4399cca52fad1e589beede54e09e5512 100644
--- a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
+++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.yaml
@@ -1,7 +1,7 @@
 # SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq5-olb.yaml#
+$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq-olb.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
 title: Mobileye EyeQ SoC system controller

-- 
2.51.0

[PATCH 02/19] dt-bindings: clock: mobileye: rename to eyeq-clk.h

[Benoît Monin]

Rename the header from mobileye,eyeq5-clk.h to mobileye,eyeq-clk.h as
it covers more SoCs than just the eyeQ5, but also the eyeQ6L and
eyeQ6H.

Also changes all includes to point to the renamed header.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 MAINTAINERS                                                           | 2 +-
 arch/mips/boot/dts/mobileye/eyeq5.dtsi                                | 2 +-
 arch/mips/boot/dts/mobileye/eyeq6h.dtsi                               | 2 +-
 drivers/clk/clk-eyeq.c                                                | 2 +-
 .../dt-bindings/clock/{mobileye,eyeq5-clk.h => mobileye,eyeq-clk.h}   | 4 ++--
 5 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 6dcfbd11efef87927041f5cf58d70633dbb4b18d..c56f17e4c585fe3e719fbae18b70a0c132c5da48 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17112,7 +17112,7 @@ F:	arch/mips/mobileye/board-epm5.its.S
 F:	drivers/clk/clk-eyeq.c
 F:	drivers/pinctrl/pinctrl-eyeq5.c
 F:	drivers/reset/reset-eyeq.c
-F:	include/dt-bindings/clock/mobileye,eyeq5-clk.h
+F:	include/dt-bindings/clock/mobileye,eyeq-clk.h
 
 MODULE SUPPORT
 M:	Luis Chamberlain <mcgrof@kernel.org>
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index 36a73e8a63a1ab32d1c300d17c4491b175428cdf..206afeff80ccf618fae80a832ee2268cad598f71 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -5,7 +5,7 @@
 
 #include <dt-bindings/interrupt-controller/mips-gic.h>
 
-#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+#include <dt-bindings/clock/mobileye,eyeq-clk.h>
 
 / {
 	#address-cells = <2>;
diff --git a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
index 5ae939d25ea87ddc15cb848c249beed3d07e32e0..a6ffdf1764b3e66295ee17b2d0d2eee8024f95f3 100644
--- a/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq6h.dtsi
@@ -5,7 +5,7 @@
 
 #include <dt-bindings/interrupt-controller/mips-gic.h>
 
-#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+#include <dt-bindings/clock/mobileye,eyeq-clk.h>
 
 / {
 	#address-cells = <2>;
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index ea1c3d78e7cd47c2698483f58ae1d691ce6d399d..8fbc8eb31185a9e82216a38a81dfbdaa1a700858 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -44,7 +44,7 @@
 #include <linux/spinlock.h>
 #include <linux/types.h>
 
-#include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+#include <dt-bindings/clock/mobileye,eyeq-clk.h>
 
 /* In frac mode, it enables fractional noise canceling DAC. Else, no function. */
 #define PCSR0_DAC_EN			BIT(0)
diff --git a/include/dt-bindings/clock/mobileye,eyeq5-clk.h b/include/dt-bindings/clock/mobileye,eyeq-clk.h
similarity index 93%
rename from include/dt-bindings/clock/mobileye,eyeq5-clk.h
rename to include/dt-bindings/clock/mobileye,eyeq-clk.h
index f353c2988035f7c9fb84e4b59c6c4a220436454b..8424ec59a02d037ddd5b049cb4b7f26764ae2542 100644
--- a/include/dt-bindings/clock/mobileye,eyeq5-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq-clk.h
@@ -3,8 +3,8 @@
  * Copyright (C) 2024 Mobileye Vision Technologies Ltd.
  */
 
-#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
-#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ5_CLK_H
+#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ_CLK_H
+#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ_CLK_H
 
 #define EQ5C_PLL_CPU		0
 #define EQ5C_PLL_VMP		1

-- 
2.51.0

[PATCH 03/19] dt-bindings: soc: mobileye: add eyeQ7H compatibles

[Benoît Monin]

The eyeQ7H features 14 OLB. The main differences with the previous
generation of SoC is that some blocks have two clock sources instead
of one and that the clock source can be the one of the clock output of
another OLB instead of the main oscillator.

For the blocks with a single parent clock, the name if that clock is
"ref", similar to what is done for the OLB of the previous SoC. The
blocks with two parent clocks use the names of the reference clocks
generated by the other OLB or the main oscillator.

Some OLB also contain a reset controller with one or more reset domain,
like the blocks found in the eyeQ6H.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 .../bindings/soc/mobileye/mobileye,eyeq-olb.yaml   | 135 ++++++++++++++++++++-
 1 file changed, 130 insertions(+), 5 deletions(-)

diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.yaml
index a1fb33ab4399cca52fad1e589beede54e09e5512..5800396d39f050c11fa5a4013297f756b97a2b02 100644
--- a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.yaml
+++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq-olb.yaml
@@ -14,7 +14,7 @@ maintainers:
 description:
   OLB ("Other Logic Block") is a hardware block grouping smaller blocks. Clocks,
   resets, pinctrl are being handled from here. EyeQ5 and EyeQ6L host a single
-  instance. EyeQ6H hosts seven instances.
+  instance. EyeQ6H hosts seven instances. EyeQ7H hosts 14 instances.
 
 properties:
   compatible:
@@ -29,6 +29,20 @@ properties:
           - mobileye,eyeq6h-south-olb
           - mobileye,eyeq6h-ddr0-olb
           - mobileye,eyeq6h-ddr1-olb
+          - mobileye,eyeq7h-south-olb
+          - mobileye,eyeq7h-east-olb
+          - mobileye,eyeq7h-west-olb
+          - mobileye,eyeq7h-periph-east-olb
+          - mobileye,eyeq7h-periph-west-olb
+          - mobileye,eyeq7h-ddr0-olb
+          - mobileye,eyeq7h-ddr1-olb
+          - mobileye,eyeq7h-mips0-olb
+          - mobileye,eyeq7h-mips1-olb
+          - mobileye,eyeq7h-mips2-olb
+          - mobileye,eyeq7h-acc0-olb
+          - mobileye,eyeq7h-acc1-olb
+          - mobileye,eyeq7h-xnn0-olb
+          - mobileye,eyeq7h-xnn1-olb
       - const: syscon
 
   reg:
@@ -44,12 +58,12 @@ properties:
     const: 1
 
   clocks:
-    maxItems: 1
-    description:
-      Input parent clock to all PLLs. Expected to be the main crystal.
+    minItems: 1
+    maxItems: 2
 
   clock-names:
-    const: ref
+    minItems: 1
+    maxItems: 2
 
 patternProperties:
   '-pins?$':
@@ -265,6 +279,88 @@ required:
 additionalProperties: false
 
 allOf:
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - mobileye,eyeq5-olb
+              - mobileye,eyeq6l-olb
+              - mobileye,eyeq6h-acc-olb
+              - mobileye,eyeq6h-central-olb
+              - mobileye,eyeq6h-east-olb
+              - mobileye,eyeq6h-west-olb
+              - mobileye,eyeq6h-south-olb
+              - mobileye,eyeq6h-ddr0-olb
+              - mobileye,eyeq6h-ddr1-olb
+              - mobileye,eyeq7h-south-olb
+              - mobileye,eyeq7h-periph-east-olb
+              - mobileye,eyeq7h-ddr0-olb
+              - mobileye,eyeq7h-ddr1-olb
+              - mobileye,eyeq7h-mips0-olb
+              - mobileye,eyeq7h-mips1-olb
+              - mobileye,eyeq7h-mips2-olb
+    then:
+      properties:
+        clocks:
+          minItems: 1
+          maxItems: 1
+        clock-names:
+          items:
+            - const: ref
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - mobileye,eyeq7h-east-olb
+              - mobileye,eyeq7h-west-olb
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: ref
+            - const: ref_100p0
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - mobileye,eyeq7h-periph-west-olb
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: ref_100p0
+            - const: ref_106p6_w
+
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - mobileye,eyeq7h-acc0-olb
+              - mobileye,eyeq7h-acc1-olb
+              - mobileye,eyeq7h-xnn0-olb
+              - mobileye,eyeq7h-xnn1-olb
+    then:
+      properties:
+        clocks:
+          minItems: 2
+          maxItems: 2
+        clock-names:
+          items:
+            - const: ref_100p0
+            - const: ref_106p6_e
+
     # Compatibles exposing a single reset domain.
   - if:
       properties:
@@ -274,6 +370,12 @@ allOf:
               - mobileye,eyeq6h-acc-olb
               - mobileye,eyeq6h-east-olb
               - mobileye,eyeq6h-west-olb
+              - mobileye,eyeq7h-east-olb
+              - mobileye,eyeq7h-west-olb
+              - mobileye,eyeq7h-periph-east-olb
+              - mobileye,eyeq7h-periph-west-olb
+              - mobileye,eyeq7h-ddr0-olb
+              - mobileye,eyeq7h-ddr1-olb
     then:
       properties:
         '#reset-cells':
@@ -289,6 +391,11 @@ allOf:
             enum:
               - mobileye,eyeq5-olb
               - mobileye,eyeq6l-olb
+              - mobileye,eyeq7h-south-olb
+              - mobileye,eyeq7h-acc0-olb
+              - mobileye,eyeq7h-acc1-olb
+              - mobileye,eyeq7h-xnn0-olb
+              - mobileye,eyeq7h-xnn1-olb
     then:
       properties:
         '#reset-cells':
@@ -306,6 +413,9 @@ allOf:
               - mobileye,eyeq6h-south-olb
               - mobileye,eyeq6h-ddr0-olb
               - mobileye,eyeq6h-ddr1-olb
+              - mobileye,eyeq7h-mips0-olb
+              - mobileye,eyeq7h-mips1-olb
+              - mobileye,eyeq7h-mips2-olb
     then:
       properties:
         '#reset-cells': false
@@ -350,3 +460,18 @@ examples:
         clock-names = "ref";
       };
     };
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      system-controller0@45000000 {
+        compatible = "mobileye,eyeq7h-acc0-olb", "syscon";
+        reg = <0x0 0x45000000 0x0 0x1000>;
+        #reset-cells = <2>;
+        #clock-cells = <1>;
+        clocks = <&olb_south 7>,
+                 <&olb_east 5>;
+        clock-names = "ref_100p0", "ref_106p6_e";
+      };
+    };

-- 
2.51.0

[PATCH 04/19] dt-bindings: clock: mobileye: add eyeQ7H clock indexes

[Benoît Monin]

Add the clock indexes for the various OLB found in the eyeQ7H SoC.
For some of the OLB, the indexes are common between two or three
blocks:
* EQ7HC_DDR defines the clock indexes of DDR0 and DDR1 OLB.
* EQ7HC_MIPS defines the clock indexes of MIPS0, MIPS1, and MIPS2 OLB.
* EQ7HC_ACC defines the clock indexes of ACC0 and ACC1 OLB.
* EQ7HC_XNN defines the clock indexes of XNN0 and XNN1 OLB.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 include/dt-bindings/clock/mobileye,eyeq-clk.h | 110 ++++++++++++++++++++++++++
 1 file changed, 110 insertions(+)

diff --git a/include/dt-bindings/clock/mobileye,eyeq-clk.h b/include/dt-bindings/clock/mobileye,eyeq-clk.h
index 8424ec59a02d037ddd5b049cb4b7f26764ae2542..0fe9b98c940cbc479ce46fc83fc651101bf1b86a 100644
--- a/include/dt-bindings/clock/mobileye,eyeq-clk.h
+++ b/include/dt-bindings/clock/mobileye,eyeq-clk.h
@@ -62,4 +62,114 @@
 #define EQ6HC_ACC_PLL_MPC		3
 #define EQ6HC_ACC_PLL_NOC		4
 
+#define EQ7HC_SOUTH_PLL_XSPI	0
+#define EQ7HC_SOUTH_PLL_VDIO	1
+#define EQ7HC_SOUTH_PLL_PER	2
+#define EQ7HC_SOUTH_PLL_100P0	3
+
+#define EQ7HC_SOUTH_DIV_VDO_DSI_SYS	4
+#define EQ7HC_SOUTH_DIV_PMA_CMN_REF	5
+#define EQ7HC_SOUTH_DIV_REF_UFS		6
+#define EQ7HC_SOUTH_DIV_REF_100P0	7
+#define EQ7HC_SOUTH_DIV_XSPI_SYS	8
+#define EQ7HC_SOUTH_DIV_XSPI_MBITS	9
+#define EQ7HC_SOUTH_DIV_NOC_S		10
+#define EQ7HC_SOUTH_DIV_PCIE_SYS	11
+#define EQ7HC_SOUTH_DIV_PCIE_SYS_MBITS	12
+#define EQ7HC_SOUTH_DIV_PCIE_GBE_PHY	13
+#define EQ7HC_SOUTH_DIV_UFS_CORE	14
+#define EQ7HC_SOUTH_DIV_UFS_SMS		15
+#define EQ7HC_SOUTH_DIV_UFS_ROM_SMS	16
+#define EQ7HC_SOUTH_DIV_ETH_SYS		17
+#define EQ7HC_SOUTH_DIV_ETH_MBITS	18
+#define EQ7HC_SOUTH_DIV_CFG_S		19
+#define EQ7HC_SOUTH_DIV_TSU		20
+#define EQ7HC_SOUTH_DIV_VDIO		21
+#define EQ7HC_SOUTH_DIV_VDIO_CORE	22
+#define EQ7HC_SOUTH_DIV_VDIO_CORE_MBIT	23
+#define EQ7HC_SOUTH_DIV_VDO_CORE_MBITS	24
+#define EQ7HC_SOUTH_DIV_VDO_P		25
+#define EQ7HC_SOUTH_DIV_VDIO_CFG	26
+#define EQ7HC_SOUTH_DIV_VDIO_TXCLKESC	27
+
+#define EQ7HC_EAST_PLL_106P6	0
+#define EQ7HC_EAST_PLL_NOC	1
+#define EQ7HC_EAST_PLL_ISP	2
+#define EQ7HC_EAST_PLL_VEU	3
+
+#define EQ7HC_EAST_DIV_REF_DDR_PHY	4
+#define EQ7HC_EAST_DIV_REF_106P6	5
+#define EQ7HC_EAST_DIV_CORE		6
+#define EQ7HC_EAST_DIV_CORE_MBITS	7
+#define EQ7HC_EAST_DIV_ISRAM_MBITS	8
+#define EQ7HC_EAST_DIV_CFG		9
+#define EQ7HC_EAST_DIV_VEU_CORE		10
+#define EQ7HC_EAST_DIV_VEU_MBITS	11
+#define EQ7HC_EAST_DIV_VEU_OCP		12
+#define EQ7HC_EAST_DIV_LBITS		13
+#define EQ7HC_EAST_DIV_ISP0_CORE	14
+
+#define EQ7HC_WEST_PLL_106P6	0
+#define EQ7HC_WEST_PLL_NOC	1
+#define EQ7HC_WEST_PLL_GPU	2
+#define EQ7HC_WEST_PLL_SSI	3
+
+#define EQ7HC_WEST_DIV_GPU		4
+#define EQ7HC_WEST_DIV_GPU_MBITS	5
+#define EQ7HC_WEST_DIV_LBITS		6
+#define EQ7HC_WEST_DIV_MIPS_TIMER	7
+#define EQ7HC_WEST_DIV_SSI_CORE		8
+#define EQ7HC_WEST_DIV_SSI_CORE_MBITS	9
+#define EQ7HC_WEST_DIV_SSI_ROM		10
+#define EQ7HC_WEST_DIV_SSI_ROM_MBITS	11
+#define EQ7HC_WEST_DIV_REF_DDR_PHY	12
+#define EQ7HC_WEST_DIV_REF_106P6	13
+#define EQ7HC_WEST_DIV_CORE		14
+#define EQ7HC_WEST_DIV_CORE_MBIT	15
+#define EQ7HC_WEST_DIV_CFG		16
+#define EQ7HC_WEST_DIV_CAU		17
+#define EQ7HC_WEST_DIV_CAU_MBITS	18
+
+#define EQ7HC_PERIPH_EAST_PLL_PER	0
+
+#define EQ7HC_PERIPH_EAST_DIV_PER	1
+
+#define EQ7HC_PERIPH_WEST_PLL_PER	0
+#define EQ7HC_PERIPH_WEST_PLL_I2S	1
+
+#define EQ7HC_PERIPH_WEST_DIV_PER	2
+#define EQ7HC_PERIPH_WEST_DIV_I2S	3
+
+#define EQ7HC_DDR_PLL		0
+
+#define EQ7HC_DDR_DIV_APB	1
+#define EQ7HC_DDR_DIV_PLLREF	2
+#define EQ7HC_DDR_DIV_DFI	3
+
+#define EQ7HC_MIPS_PLL_CPU	0
+
+#define EQ7HC_MIPS_DIV_CM	1
+
+#define EQ7HC_ACC_PLL_VMP	0
+#define EQ7HC_ACC_PLL_MPC	1
+#define EQ7HC_ACC_PLL_PMA	2
+#define EQ7HC_ACC_PLL_NOC	3
+
+#define EQ7HC_ACC_DIV_PMA	4
+#define EQ7HC_ACC_DIV_NCORE	5
+#define EQ7HC_ACC_DIV_CFG	6
+
+#define EQ7HC_XNN_PLL_XNN0	0
+#define EQ7HC_XNN_PLL_XNN1	1
+#define EQ7HC_XNN_PLL_XNN2	2
+#define EQ7HC_XNN_PLL_CLSTR	3
+
+#define EQ7HC_XNN_DIV_XNN0	4
+#define EQ7HC_XNN_DIV_XNN1	5
+#define EQ7HC_XNN_DIV_XNN2	6
+#define EQ7HC_XNN_DIV_CLSTR	7
+#define EQ7HC_XNN_DIV_I2	8
+#define EQ7HC_XNN_DIV_I2_SMS	9
+#define EQ7HC_XNN_DIV_CFG	10
+
 #endif

-- 
2.51.0

[PATCH 05/19] dt-bindings: reset: add Mobileye eyeQ

[Benoît Monin]

Define the indexes of the reset controllers present in 11 of the OLB
found in Mobileye eyeQ7H SoC. The define names start with EQ7HR, which
is the abbreviation of EyeQ7H Reset.

For the OLBs with multiple reset domains, the domain number is in the
define name (DOMx) and should also be passed in the device tree:

    resets = <&olb_south 0 EQ7HR_SOUTH_DOM0_PCI_CTL>;

For the OLBs with a single reset domain, only the reset index is needed:

    resets = <&olb_periph_west EQ7HR_PERIPH_UART>;

Some reset indexes are common between two OLB:
* EQ7HR_PERIPH defines the reset indexes of OLB periph_east and
  periph_west.
* EQ7HR_DDR defines the reset indexes of OLB ddr0 and ddr1.
* EQ7HR_ACC defines the reset indexes of OLB acc0 and acc1.
* EQ7HR_XNN defines the reset indexes of OLB xnn0 and xnn1.

Signed-off-by: Sari Khoury <sari.khoury@mobileye.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 MAINTAINERS                                     |  1 +
 include/dt-bindings/reset/mobileye,eyeq-reset.h | 75 +++++++++++++++++++++++++
 2 files changed, 76 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index c56f17e4c585fe3e719fbae18b70a0c132c5da48..6e6bf23e988ad9b8d77268f680ea4dee0489684f 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17113,6 +17113,7 @@ F:	drivers/clk/clk-eyeq.c
 F:	drivers/pinctrl/pinctrl-eyeq5.c
 F:	drivers/reset/reset-eyeq.c
 F:	include/dt-bindings/clock/mobileye,eyeq-clk.h
+F:	include/dt-bindings/reset/mobileye,eyeq-reset.h
 
 MODULE SUPPORT
 M:	Luis Chamberlain <mcgrof@kernel.org>
diff --git a/include/dt-bindings/reset/mobileye,eyeq-reset.h b/include/dt-bindings/reset/mobileye,eyeq-reset.h
new file mode 100644
index 0000000000000000000000000000000000000000..70d3b7140f8d2599186c7ddff32b8131e90c644e
--- /dev/null
+++ b/include/dt-bindings/reset/mobileye,eyeq-reset.h
@@ -0,0 +1,75 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2024 Mobileye Vision Technologies Ltd.
+ */
+
+#ifndef _DT_BINDINGS_MOBILEYE_EYEQ_RESET_H
+#define _DT_BINDINGS_MOBILEYE_EYEQ_RESET_H
+
+#define EQ7HR_SOUTH_DOM0_PCI_PHY	0
+#define EQ7HR_SOUTH_DOM0_PCI_CTL	1
+#define EQ7HR_SOUTH_DOM0_S_NOC		2
+#define EQ7HR_SOUTH_DOM0_GBE_PHY	3
+#define EQ7HR_SOUTH_DOM0_GBE_CTL	4
+
+#define EQ7HR_SOUTH_DOM1_XSPI		0
+#define EQ7HR_SOUTH_DOM1_UFS		1
+#define EQ7HR_SOUTH_DOM1_S_VDIO		2
+
+#define EQ7HR_EAST_ISP			0
+#define EQ7HR_EAST_VEU			1
+#define EQ7HR_EAST_LBIST		2
+
+#define EQ7HR_WEST_GPU			0
+#define EQ7HR_WEST_CAU			1
+#define EQ7HR_WEST_LBIST		2
+#define EQ7HR_WEST_GPU_LBIST		3
+
+#define EQ7HR_PERIPH_GPIO		0
+#define EQ7HR_PERIPH_EXT		1
+#define EQ7HR_PERIPH_UART		2
+#define EQ7HR_PERIPH_SPI		3
+#define EQ7HR_PERIPH_I2C0		4
+#define EQ7HR_PERIPH_I2C1		5
+#define EQ7HR_PERIPH_I2C2		6
+#define EQ7HR_PERIPH_I2S		7
+
+#define EQ7HR_DDR_APB			0
+#define EQ7HR_DDR_DMI			1
+#define EQ7HR_DDR_DFI			2
+#define EQ7HR_DDR_PHY_SMS		3
+#define EQ7HR_DDR_CTL_SMS		4
+
+#define EQ7HR_ACC_DOM0_VMP0		0
+#define EQ7HR_ACC_DOM0_VMP1		1
+#define EQ7HR_ACC_DOM0_VMP2		2
+#define EQ7HR_ACC_DOM0_VMP3		3
+#define EQ7HR_ACC_DOM0_MPC0		4
+#define EQ7HR_ACC_DOM0_MPC1		5
+#define EQ7HR_ACC_DOM0_PMA0		6
+#define EQ7HR_ACC_DOM0_PMA1		7
+
+#define EQ7HR_ACC_DOM1_NCORE0		0
+#define EQ7HR_ACC_DOM1_NCORE1		1
+#define EQ7HR_ACC_DOM1_NCORE0_M		2
+#define EQ7HR_ACC_DOM1_NCORE1_M		3
+#define EQ7HR_ACC_DOM1_NCORE_NOC	4
+#define EQ7HR_ACC_DOM1_VMP_NOC		5
+#define EQ7HR_ACC_DOM1_MPC_NOC		6
+#define EQ7HR_ACC_DOM1_PMA_NOC		7
+
+#define EQ7HR_XNN_DOM0_XNN0		0
+#define EQ7HR_XNN_DOM0_XNN1		1
+#define EQ7HR_XNN_DOM0_XNN2		2
+
+#define EQ7HR_XNN_DOM1_XNN0		0
+#define EQ7HR_XNN_DOM1_XNN1		1
+#define EQ7HR_XNN_DOM1_XNN2		2
+#define EQ7HR_XNN_DOM1_XNN3		3
+#define EQ7HR_XNN_DOM1_NCORE		4
+#define EQ7HR_XNN_DOM1_I2_0		5
+#define EQ7HR_XNN_DOM1_I2_1		6
+#define EQ7HR_XNN_DOM1_SMS_0		7
+#define EQ7HR_XNN_DOM1_SMS_1		8
+
+#endif

-- 
2.51.0

[PATCH 06/19] reset: eyeq: add eyeQ7H compatibles

[Benoît Monin]

Add support for the reset controllers found in the eyeQ7H OLB. For
this, three new types of reset domain are added to the driver.

The EQR_EYEQ7H_ACRP reset domain is similar to the EQR_EYEQ5_ACRP
domain with a different registers layout.

The EQR_EYEQ7H_CFG reset domain is similar to the EQR_EYEQ5_PCIE
domain, again with a different registers layout.

The EQR_EYEQ7H_ACC reset domain is similar to the EQR_EYEQ6H_SARCR
domain, with a different registers layout and no busy waiting.

Signed-off-by: Sari Khoury <sari.khoury@mobileye.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/reset/reset-eyeq.c | 248 ++++++++++++++++++++++++++++++++++++++++++++-
 1 file changed, 246 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/reset-eyeq.c b/drivers/reset/reset-eyeq.c
index 02d50041048b42921e3e511148cd29f215b5fc5e..322c05d7e6b818e5b0d395787c69ad91616820e0 100644
--- a/drivers/reset/reset-eyeq.c
+++ b/drivers/reset/reset-eyeq.c
@@ -1,10 +1,11 @@
 // SPDX-License-Identifier: GPL-2.0-only
 /*
- * Reset driver for the Mobileye EyeQ5, EyeQ6L and EyeQ6H platforms.
+ * Reset driver for the Mobileye EyeQ5, EyeQ6L, EyeQ6H and EyeQ7H platforms.
  *
  * Controllers live in a shared register region called OLB. EyeQ5 and EyeQ6L
  * have a single OLB instance for a single reset controller. EyeQ6H has seven
- * OLB instances; three host reset controllers.
+ * OLB instances; three host reset controllers. EyeQ7H has fourteen OLB instances;
+ * eleven host reset controllers.
  *
  * Each reset controller has one or more domain. Domains are of a given type
  * (see enum eqr_domain_type), with a valid offset mask (up to 32 resets per
@@ -61,6 +62,40 @@
  *  9. PMA0	10. PMA1	11. MPC0	12. MPC1
  * 13. MPC2	14. MPC3	15. PERIPH
  *
+ * Known resets in EyeQ7H south (type EQR_EYEQ7H_CFG)
+ *  0. PCI_PHY	1. PCI_CTL	2. S_NOC	3. GBE_PHY
+ *  4. GBE_CTL	5. XSPI		6. UFS		7. VDIO
+ *
+ * Known resets in EyeQ7H east (type EQR_EYEQ7H_CFG)
+ *  0. ISP	2. VEU		3. LBIST
+ *
+ * Known resets in EyeQ7H west (type EQR_EYEQ7H_CFG)
+ *  0. GPU	2. CAU		3. LBIST	4. GPU_LBIST
+ *
+ * Known resets in EyeQ7H periph (type EQR_EYEQ5_SARCR)
+ *  0. gpio	1.EXT TIMER	3.UART		4. SPI
+ *  5. I2C0	6. I2C1		7.I2C2		8. I2S
+ *
+ * Known resets in EyeQ7H ddr (type EQR_EYEQ7H_CFG)
+ *  0. APB	2. DMI		3. DFI		4. PHY_SMS
+ *  5. CTL_SMS
+ *
+ * Known resets in EyeQ7H acc (type EQR_EYEQ7H_ACRP)
+ *  1. VMP0	2. XVMP1	3. VMP2		4. VMP3
+ *  5. MPC0	6. MPC1		7. PMA0		8. PMA1
+ *
+ * Known resets in EyeQ7H acc (type EQR_EYEQ7H_ACC)
+ *  1. NCORE0	 2. NCORE1	3. NCORE0_M	4. NCORE1_M
+ *  5. NCORE_NOC 6. VMP_NOC	7. MPC_NOC	8. PMA_NOC
+ *
+ * Known resets in EyeQ7H xnn (type EQR_EYEQ7H_ACRP)
+ *  1. XNN0	2. XNN1		3.XNN2
+ *
+ * Known resets in EyeQ7H xnn (type EQR_EYEQ7H_ACC)
+ *  1. XNN0	2. XNN1		3. XNN2		4. XNN3
+ *  5. NCORE	6. I2_0		7. I2_1		8. SMS_0
+ *  9. SMS_1
+ *
  * Abbreviations:
  *  - PMA: Programmable Macro Array
  *  - MPC: Multi-threaded Processing Clusters
@@ -102,6 +137,9 @@ enum eqr_domain_type {
 	EQR_EYEQ5_ACRP,
 	EQR_EYEQ5_PCIE,
 	EQR_EYEQ6H_SARCR,
+	EQR_EYEQ7H_ACRP,
+	EQR_EYEQ7H_CFG,
+	EQR_EYEQ7H_ACC
 };
 
 /*
@@ -126,6 +164,21 @@ enum eqr_domain_type {
 #define EQR_EYEQ6H_SARCR_RST_STATUS	(0x008)
 #define EQR_EYEQ6H_SARCR_CLK_REQUEST	(0x00C)
 
+/*
+ * Domain type EQR_EYEQ7H_ACRP register masks.
+ * Registers are: base + 4 * offset.
+ */
+#define EQR_EYEQ7H_ACRP_PD_REQ		BIT(0)
+#define EQR_EYEQ7H_ACRP_MBIST_CFG	GENMASK(3, 1)
+#define EQR_EYEQ7H_ACRP_ST_POWER_DOWN	BIT(13)
+#define EQR_EYEQ7H_ACRP_ST_ACTIVE	BIT(14)
+
+/*
+ * Domain type EQR_EYEQ7H_ACC register masks.
+ */
+#define EQR_EYEQ7H_ACC_CLK_EN		(0x000)
+#define EQR_EYEQ7H_ACC_RST_EN		(0x004)
+
 struct eqr_busy_wait_timings {
 	unsigned long sleep_us;
 	unsigned long timeout_us;
@@ -134,7 +187,10 @@ struct eqr_busy_wait_timings {
 static const struct eqr_busy_wait_timings eqr_timings[] = {
 	[EQR_EYEQ5_SARCR]	= {1, 10},
 	[EQR_EYEQ5_ACRP]	= {1, 40 * USEC_PER_MSEC}, /* LBIST implies long timeout. */
+	[EQR_EYEQ7H_ACRP]	= {1, 40 * USEC_PER_MSEC},
 	/* EQR_EYEQ5_PCIE does no busy waiting. */
+	/* EQR_EYEQ7H_CFG does no busy waiting. */
+	/* EQR_EYEQ7H_ACC does no busy waiting. */
 	[EQR_EYEQ6H_SARCR]	= {1, 400},
 };
 
@@ -209,6 +265,17 @@ static int eqr_busy_wait_locked(struct eqr_private *priv, struct device *dev,
 					 sleep_us, timeout_us);
 		break;
 
+	case EQR_EYEQ7H_ACRP:
+		reg = base + 4 * offset;
+		if (assert)
+			mask = EQR_EYEQ7H_ACRP_ST_POWER_DOWN;
+		else
+			mask = EQR_EYEQ7H_ACRP_ST_ACTIVE;
+
+		ret = readl_poll_timeout(reg, val, !!(val & mask),
+					 sleep_us, timeout_us);
+		break;
+
 	case EQR_EYEQ5_PCIE:
 		ret = 0; /* No busy waiting. */
 		break;
@@ -229,6 +296,14 @@ static int eqr_busy_wait_locked(struct eqr_private *priv, struct device *dev,
 					&rst_status, &clk_status);
 		break;
 
+	case EQR_EYEQ7H_CFG:
+		ret = 0; /* No busy waiting. */
+		break;
+
+	case EQR_EYEQ7H_ACC:
+		ret = 0; /* No busy waiting. */
+		break;
+
 	default:
 		WARN_ON(1);
 		ret = -EINVAL;
@@ -261,6 +336,11 @@ static void eqr_assert_locked(struct eqr_private *priv, u32 domain, u32 offset)
 		writel(readl(reg) | EQR_EYEQ5_ACRP_PD_REQ, reg);
 		break;
 
+	case EQR_EYEQ7H_ACRP:
+		reg = base + 4 * offset;
+		writel((readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG) | EQR_EYEQ7H_ACRP_PD_REQ, reg);
+		break;
+
 	case EQR_EYEQ5_PCIE:
 		writel(readl(base) & ~BIT(offset), base);
 		break;
@@ -273,6 +353,18 @@ static void eqr_assert_locked(struct eqr_private *priv, u32 domain, u32 offset)
 		writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST);
 		break;
 
+	case EQR_EYEQ7H_CFG:
+		writel(readl(base) & ~BIT(2 * offset) & ~BIT(2 * offset + 1), base);
+		break;
+
+	case EQR_EYEQ7H_ACC:
+		/* RST_REQUEST and CLK_REQUEST must be kept in sync. */
+		val = readl(base + EQR_EYEQ7H_ACC_RST_EN);
+		val &= ~BIT(offset);
+		writel(val, base + EQR_EYEQ7H_ACC_RST_EN);
+		writel(val, base + EQR_EYEQ7H_ACC_CLK_EN);
+		break;
+
 	default:
 		WARN_ON(1);
 		break;
@@ -315,6 +407,11 @@ static void eqr_deassert_locked(struct eqr_private *priv, u32 domain,
 		writel(readl(reg) & ~EQR_EYEQ5_ACRP_PD_REQ, reg);
 		break;
 
+	case EQR_EYEQ7H_ACRP:
+		reg = base + 4 * offset;
+		writel((readl(reg) & ~EQR_EYEQ7H_ACRP_MBIST_CFG) & ~EQR_EYEQ7H_ACRP_PD_REQ, reg);
+		break;
+
 	case EQR_EYEQ5_PCIE:
 		writel(readl(base) | BIT(offset), base);
 		break;
@@ -327,6 +424,18 @@ static void eqr_deassert_locked(struct eqr_private *priv, u32 domain,
 		writel(val, base + EQR_EYEQ6H_SARCR_CLK_REQUEST);
 		break;
 
+	case EQR_EYEQ7H_CFG:
+		writel(readl(base) | BIT(2 * offset) | BIT(2 * offset + 1), base);
+		break;
+
+	case EQR_EYEQ7H_ACC:
+		/* RST_REQUEST and CLK_REQUEST must be kept in sync. */
+		val = readl(base + EQR_EYEQ7H_ACC_RST_EN);
+		val |= BIT(offset);
+		writel(val, base + EQR_EYEQ7H_ACC_RST_EN);
+		writel(val, base + EQR_EYEQ7H_ACC_CLK_EN);
+		break;
+
 	default:
 		WARN_ON(1);
 		break;
@@ -368,11 +477,19 @@ static int eqr_status(struct reset_controller_dev *rcdev, unsigned long id)
 	case EQR_EYEQ5_ACRP:
 		reg = base + 4 * offset;
 		return !(readl(reg) & EQR_EYEQ5_ACRP_ST_ACTIVE);
+	case EQR_EYEQ7H_ACRP:
+		reg = base + 4 * offset;
+		return !(readl(reg) & EQR_EYEQ7H_ACRP_ST_ACTIVE);
 	case EQR_EYEQ5_PCIE:
 		return !(readl(base) & BIT(offset));
 	case EQR_EYEQ6H_SARCR:
 		reg = base + EQR_EYEQ6H_SARCR_RST_STATUS;
 		return !(readl(reg) & BIT(offset));
+	case EQR_EYEQ7H_CFG:
+		return !(readl(base) & BIT(2 * offset));
+	case EQR_EYEQ7H_ACC:
+		reg = base + EQR_EYEQ7H_ACC_RST_EN;
+		return !(readl(reg) & BIT(offset));
 	default:
 		return -EINVAL;
 	}
@@ -537,6 +654,113 @@ static const struct eqr_match_data eqr_eyeq6h_acc_data = {
 	.domains	= eqr_eyeq6h_acc_domains,
 };
 
+static const struct eqr_domain_descriptor eqr_eyeq7h_south_domains[] = {
+	{
+		.type = EQR_EYEQ7H_CFG,
+		.valid_mask = 0x1F,
+		.offset = 0x070,
+	},
+	{
+		.type = EQR_EYEQ7H_CFG,
+		.valid_mask = 0x7,
+		.offset = 0x074,
+	},
+};
+
+static const struct eqr_match_data eqr_eyeq7h_south_data = {
+	.domain_count	= ARRAY_SIZE(eqr_eyeq7h_south_domains),
+	.domains	= eqr_eyeq7h_south_domains,
+};
+
+static const struct eqr_domain_descriptor eqr_eyeq7h_east_domains[] = {
+	{
+		.type = EQR_EYEQ7H_CFG,
+		.valid_mask = 0x7,
+		.offset = 0x060,
+	},
+};
+
+static const struct eqr_match_data eqr_eyeq7h_east_data = {
+	.domain_count	= ARRAY_SIZE(eqr_eyeq7h_east_domains),
+	.domains	= eqr_eyeq7h_east_domains,
+};
+
+static const struct eqr_domain_descriptor eqr_eyeq7h_west_domains[] = {
+	{
+		.type = EQR_EYEQ7H_CFG,
+		.valid_mask = 0xf,
+		.offset = 0x068,
+	},
+};
+
+static const struct eqr_match_data eqr_eyeq7h_west_data = {
+	.domain_count	= ARRAY_SIZE(eqr_eyeq7h_west_domains),
+	.domains	= eqr_eyeq7h_west_domains,
+};
+
+/* Periph OLBs each have an instance. */
+static const struct eqr_domain_descriptor eqr_eyeq7h_per_domains[] = {
+	{
+		.type = EQR_EYEQ6H_SARCR,
+		.valid_mask = 0xFF,
+		.offset = 0x030,
+	},
+};
+
+static const struct eqr_match_data eqr_eyeq7h_per_data = {
+	.domain_count	= ARRAY_SIZE(eqr_eyeq7h_per_domains),
+	.domains	= eqr_eyeq7h_per_domains,
+};
+
+static const struct eqr_domain_descriptor eqr_eyeq7h_ddr_domains[] = {
+	{
+		.type = EQR_EYEQ7H_ACRP,
+		.valid_mask = 0x1F,
+		.offset = 0x008,
+	},
+};
+
+static const struct eqr_match_data eqr_eyeq7h_ddr_data = {
+	.domain_count	= ARRAY_SIZE(eqr_eyeq7h_ddr_domains),
+	.domains	= eqr_eyeq7h_ddr_domains,
+};
+
+static const struct eqr_domain_descriptor eqr_eyeq7h_acc_domains[] = {
+	{
+		.type = EQR_EYEQ7H_ACRP,
+		.valid_mask = 0xFF,
+		.offset = 0x000,
+	},
+	{
+		.type = EQR_EYEQ7H_ACC,
+		.valid_mask = 0xFF,
+		.offset = 0x060,
+	},
+};
+
+static const struct eqr_match_data eqr_eyeq7h_acc_data = {
+	.domain_count	= ARRAY_SIZE(eqr_eyeq7h_acc_domains),
+	.domains	= eqr_eyeq7h_acc_domains,
+};
+
+static const struct eqr_domain_descriptor eqr_eyeq7h_xnn_domains[] = {
+	{
+		.type = EQR_EYEQ7H_ACRP,
+		.valid_mask = 0x7,
+		.offset = 0x000,
+	},
+	{
+		.type = EQR_EYEQ7H_ACC,
+		.valid_mask = 0x1FF,
+		.offset = 0x060,
+	},
+};
+
+static const struct eqr_match_data eqr_eyeq7h_xnn_data = {
+	.domain_count	= ARRAY_SIZE(eqr_eyeq7h_xnn_domains),
+	.domains	= eqr_eyeq7h_xnn_domains,
+};
+
 /*
  * Table describes OLB system-controller compatibles.
  * It does not get used to match against devicetree node.
@@ -547,6 +771,17 @@ static const struct of_device_id eqr_match_table[] = {
 	{ .compatible = "mobileye,eyeq6h-west-olb", .data = &eqr_eyeq6h_we_data },
 	{ .compatible = "mobileye,eyeq6h-east-olb", .data = &eqr_eyeq6h_we_data },
 	{ .compatible = "mobileye,eyeq6h-acc-olb", .data = &eqr_eyeq6h_acc_data },
+	{ .compatible = "mobileye,eyeq7h-south-olb", .data = &eqr_eyeq7h_south_data },
+	{ .compatible = "mobileye,eyeq7h-east-olb", .data = &eqr_eyeq7h_east_data },
+	{ .compatible = "mobileye,eyeq7h-west-olb", .data = &eqr_eyeq7h_west_data },
+	{ .compatible = "mobileye,eyeq7h-periph-east-olb", .data = &eqr_eyeq7h_per_data },
+	{ .compatible = "mobileye,eyeq7h-periph-west-olb", .data = &eqr_eyeq7h_per_data },
+	{ .compatible = "mobileye,eyeq7h-ddr0-olb", .data = &eqr_eyeq7h_ddr_data },
+	{ .compatible = "mobileye,eyeq7h-ddr1-olb", .data = &eqr_eyeq7h_ddr_data },
+	{ .compatible = "mobileye,eyeq7h-acc0-olb", .data = &eqr_eyeq7h_acc_data },
+	{ .compatible = "mobileye,eyeq7h-acc1-olb", .data = &eqr_eyeq7h_acc_data },
+	{ .compatible = "mobileye,eyeq7h-xnn0-olb", .data = &eqr_eyeq7h_xnn_data },
+	{ .compatible = "mobileye,eyeq7h-xnn1-olb", .data = &eqr_eyeq7h_xnn_data },
 	{}
 };
 MODULE_DEVICE_TABLE(of, eqr_match_table);
@@ -556,6 +791,15 @@ static const struct auxiliary_device_id eqr_id_table[] = {
 	{ .name = "clk_eyeq.reset_west" },
 	{ .name = "clk_eyeq.reset_east" },
 	{ .name = "clk_eyeq.reset_acc" },
+	{ .name = "clk_eyeq.reset_south" },
+	{ .name = "clk_eyeq.reset_periph_east" },
+	{ .name = "clk_eyeq.reset_periph_west" },
+	{ .name = "clk_eyeq.reset_ddr0" },
+	{ .name = "clk_eyeq.reset_ddr1" },
+	{ .name = "clk_eyeq.reset_acc0" },
+	{ .name = "clk_eyeq.reset_acc1" },
+	{ .name = "clk_eyeq.reset_xnn0" },
+	{ .name = "clk_eyeq.reset_xnn1" },
 	{}
 };
 MODULE_DEVICE_TABLE(auxiliary, eqr_id_table);

-- 
2.51.0

[PATCH 07/19] clk: fixed-factor: add clk_hw_register_fixed_factor_with_accuracy

[Benoît Monin]

Add a variant of clk_hw_register_fixed_factor allowing to set the
accuracy of the fixed factor clock.

This function allows declaring a fixed factor with a known accuracy
and a parent clock by name.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-fixed-factor.c | 12 ++++++++++++
 include/linux/clk-provider.h   |  3 +++
 2 files changed, 15 insertions(+)

diff --git a/drivers/clk/clk-fixed-factor.c b/drivers/clk/clk-fixed-factor.c
index e62ae8794d445f685156276d5135448f340fca3f..7c76658a725f9b268da2485769979e5ba213d25b 100644
--- a/drivers/clk/clk-fixed-factor.c
+++ b/drivers/clk/clk-fixed-factor.c
@@ -217,6 +217,18 @@ struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
 }
 EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor);
 
+struct clk_hw *clk_hw_register_fixed_factor_with_accuracy(struct device *dev,
+		const char *name, const char *parent_name, unsigned long flags,
+		unsigned int mult, unsigned int div, unsigned long acc)
+{
+	const struct clk_parent_data pdata = { .index = -1 };
+
+	return __clk_hw_register_fixed_factor(dev, NULL, name, parent_name, NULL,
+					      &pdata, flags, mult, div, acc,
+					      CLK_FIXED_FACTOR_FIXED_ACCURACY, false);
+}
+EXPORT_SYMBOL_GPL(clk_hw_register_fixed_factor_with_accuracy);
+
 struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
 		struct device_node *np, const char *name, const char *fw_name,
 		unsigned long flags, unsigned int mult, unsigned int div)
diff --git a/include/linux/clk-provider.h b/include/linux/clk-provider.h
index 630705a47129453c241f1b1755f2c2f2a7ed8f77..6b3e426f5754bfae4af89765bf5abd2954ca49dc 100644
--- a/include/linux/clk-provider.h
+++ b/include/linux/clk-provider.h
@@ -1153,6 +1153,9 @@ void clk_unregister_fixed_factor(struct clk *clk);
 struct clk_hw *clk_hw_register_fixed_factor(struct device *dev,
 		const char *name, const char *parent_name, unsigned long flags,
 		unsigned int mult, unsigned int div);
+struct clk_hw *clk_hw_register_fixed_factor_with_accuracy(struct device *dev,
+		const char *name, const char *parent_name, unsigned long flags,
+		unsigned int mult, unsigned int div, unsigned long acc);
 struct clk_hw *clk_hw_register_fixed_factor_fwname(struct device *dev,
 		struct device_node *np, const char *name, const char *fw_name,
 		unsigned long flags, unsigned int mult, unsigned int div);

-- 
2.51.0

[PATCH 08/19] clk: divider: check divider validity for CLK_DIVIDER_EVEN_INTEGERS

[Benoît Monin]

Ensure that the divider is even when the flag CLK_DIVIDER_EVEN_INTEGERS
is set, similar to the power of two check for CLK_DIVIDER_POWER_OF_TWO.

Signed-off-by: Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-divider.c | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index c1f426b8a5043cb5a1de08e1da385928ec54a2ed..8e8f87024e76625f348f1d66c15a7a938fa0c4db 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -181,6 +181,8 @@ static bool _is_valid_div(const struct clk_div_table *table, unsigned int div,
 {
 	if (flags & CLK_DIVIDER_POWER_OF_TWO)
 		return is_power_of_2(div);
+	if (flags & CLK_DIVIDER_EVEN_INTEGERS)
+		return (div % 2) == 0;
 	if (table)
 		return _is_valid_table_div(table, div);
 	return true;

-- 
2.51.0

[PATCH 09/19] clk: divider: check validity of flags when a table is provided

[Benoît Monin]

If any of the flag CLK_DIVIDER_ONE_BASED, CLK_DIVIDER_POWER_OF_TWO,
CLK_DIVIDER_MAX_AT_ZERO or CLK_DIVIDER_EVEN_INTEGERS is set, the divider
table will be ignored in _get_div and _get_val. This can lead to subtle
bug when a clock is registered with some flags and an optional table,
with the clock rate and register value being computed with the wrong
type of conversion.

Prevent this by refusing to register a divider with both the flag and
the table set.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-divider.c | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c
index 8e8f87024e76625f348f1d66c15a7a938fa0c4db..b4861d519bac2121dd015d094c94a5fee2480148 100644
--- a/drivers/clk/clk-divider.c
+++ b/drivers/clk/clk-divider.c
@@ -561,6 +561,13 @@ struct clk_hw *__clk_hw_register_divider(struct device *dev,
 			return ERR_PTR(-EINVAL);
 		}
 	}
+	if (table && (clk_divider_flags & (CLK_DIVIDER_ONE_BASED |
+					   CLK_DIVIDER_POWER_OF_TWO |
+					   CLK_DIVIDER_MAX_AT_ZERO |
+					   CLK_DIVIDER_EVEN_INTEGERS))) {
+		pr_warn("divider table and flags incompatible\n");
+		return ERR_PTR(-EINVAL);
+	}
 
 	/* allocate the divider */
 	div = kzalloc(sizeof(*div), GFP_KERNEL);

-- 
2.51.0

[PATCH 10/19] clk: eyeq: skip post-divisor when computing pll divisor

[Benoît Monin]

The output of the pll is routed before the post-divisor so ignore it
when computing the frequency of the pll, functional change is
implemented to reflect how the clock signal is wired internally.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 8fbc8eb31185a9e82216a38a81dfbdaa1a700858..cbba4a21cca47efb8ab554ecf7322e47437c9c6a 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -177,8 +177,6 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
 
 	*mult = FIELD_GET(PCSR0_INTIN, r0);
 	*div = FIELD_GET(PCSR0_REF_DIV, r0);
-	if (r0 & PCSR0_FOUTPOSTDIV_EN)
-		*div *= FIELD_GET(PCSR0_POST_DIV1, r0) * FIELD_GET(PCSR0_POST_DIV2, r0);
 
 	/* Fractional mode, in 2^20 (0x100000) parts. */
 	if (r0 & PCSR0_DSM_EN) {

-- 
2.51.0

[PATCH 11/19] clk: eyeq: rename the parent field to parent_idx

[Benoît Monin]

Make some room for introducing a new field to refer to the parent clock
by its name for divisors and fixed factors.

No functional code change in this patch, this is a rename only.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 24 ++++++++++++------------
 1 file changed, 12 insertions(+), 12 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index cbba4a21cca47efb8ab554ecf7322e47437c9c6a..89e0782b5cbe16a7c2010d9d441ace139fd0deb5 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -83,7 +83,7 @@ struct eqc_pll {
 struct eqc_div {
 	unsigned int	index;
 	const char	*name;
-	unsigned int	parent;
+	unsigned int	parent_idx;
 	unsigned int	reg;
 	u8		shift;
 	u8		width;
@@ -94,7 +94,7 @@ struct eqc_fixed_factor {
 	const char	*name;
 	unsigned int	mult;
 	unsigned int	div;
-	unsigned int	parent;
+	unsigned int	parent_idx;
 };
 
 struct eqc_match_data {
@@ -269,11 +269,11 @@ static void eqc_probe_init_divs(struct device *dev, const struct eqc_match_data
 	for (i = 0; i < data->div_count; i++) {
 		div = &data->divs[i];
 		reg = base + div->reg;
-		parent = cells->hws[div->parent];
+		parent = cells->hws[div->parent_idx];
 
 		if (IS_ERR(parent)) {
 			/* Parent is in early clk provider. */
-			parent_data.index = div->parent;
+			parent_data.index = div->parent_idx;
 			parent_data.hw = NULL;
 		} else {
 			/* Avoid clock lookup when we already have the hw reference. */
@@ -301,12 +301,12 @@ static void eqc_probe_init_fixed_factors(struct device *dev,
 
 	for (i = 0; i < data->fixed_factor_count; i++) {
 		ff = &data->fixed_factors[i];
-		parent_hw = cells->hws[ff->parent];
+		parent_hw = cells->hws[ff->parent_idx];
 
 		if (IS_ERR(parent_hw)) {
 			/* Parent is in early clk provider. */
 			hw = clk_hw_register_fixed_factor_index(dev, ff->name,
-					ff->parent, 0, ff->mult, ff->div);
+					ff->parent_idx, 0, ff->mult, ff->div);
 		} else {
 			/* Avoid clock lookup when we already have the hw reference. */
 			hw = clk_hw_register_fixed_factor_parent_hw(dev, ff->name,
@@ -522,7 +522,7 @@ static const struct eqc_div eqc_eyeq5_divs[] = {
 	{
 		.index = EQ5C_DIV_OSPI,
 		.name = "div-ospi",
-		.parent = EQ5C_PLL_PER,
+		.parent_idx = EQ5C_PLL_PER,
 		.reg = 0x11C,
 		.shift = 0,
 		.width = 4,
@@ -597,7 +597,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] = {
 	{
 		.index = EQ6HC_SOUTH_DIV_EMMC,
 		.name = "div-emmc",
-		.parent = EQ6HC_SOUTH_PLL_PER,
+		.parent_idx = EQ6HC_SOUTH_PLL_PER,
 		.reg = 0x070,
 		.shift = 4,
 		.width = 4,
@@ -605,7 +605,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] = {
 	{
 		.index = EQ6HC_SOUTH_DIV_OSPI_REF,
 		.name = "div-ospi-ref",
-		.parent = EQ6HC_SOUTH_PLL_PER,
+		.parent_idx = EQ6HC_SOUTH_PLL_PER,
 		.reg = 0x090,
 		.shift = 4,
 		.width = 4,
@@ -613,7 +613,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] = {
 	{
 		.index = EQ6HC_SOUTH_DIV_OSPI_SYS,
 		.name = "div-ospi-sys",
-		.parent = EQ6HC_SOUTH_PLL_PER,
+		.parent_idx = EQ6HC_SOUTH_PLL_PER,
 		.reg = 0x090,
 		.shift = 8,
 		.width = 1,
@@ -621,7 +621,7 @@ static const struct eqc_div eqc_eyeq6h_south_divs[] = {
 	{
 		.index = EQ6HC_SOUTH_DIV_TSU,
 		.name = "div-tsu",
-		.parent = EQ6HC_SOUTH_PLL_PCIE,
+		.parent_idx = EQ6HC_SOUTH_PLL_PCIE,
 		.reg = 0x098,
 		.shift = 4,
 		.width = 8,
@@ -790,7 +790,7 @@ static void __init eqc_early_init(struct device_node *np,
 
 	for (i = 0; i < early_data->early_fixed_factor_count; i++) {
 		const struct eqc_fixed_factor *ff = &early_data->early_fixed_factors[i];
-		struct clk_hw *parent_hw = cells->hws[ff->parent];
+		struct clk_hw *parent_hw = cells->hws[ff->parent_idx];
 		struct clk_hw *hw;
 
 		hw = clk_hw_register_fixed_factor_parent_hw(NULL, ff->name,

-- 
2.51.0

[PATCH 12/19] clk: eyeq: lookup parent clock by name

[Benoît Monin]

When registering a divider or a fixed factor during probe, lookup its
parent by name if the parent clock was registered early. Looking up the
parent clock by index in this case leads to orphaned clocks or clocks
with the wrong parent, since the index refers to clocks from the device
tree.

This is applicable to the eyeQ5 where some probed dividers and fixed
factors refer to PLL and fixed factors registered in early init.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 48 ++++++++++++++++++++++++++----------------------
 1 file changed, 26 insertions(+), 22 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 89e0782b5cbe16a7c2010d9d441ace139fd0deb5..a0581016100c7367efb373a3fb3b7c6d51b49912 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -84,6 +84,7 @@ struct eqc_div {
 	unsigned int	index;
 	const char	*name;
 	unsigned int	parent_idx;
+	const char	*parent_name;
 	unsigned int	reg;
 	u8		shift;
 	u8		width;
@@ -95,6 +96,7 @@ struct eqc_fixed_factor {
 	unsigned int	mult;
 	unsigned int	div;
 	unsigned int	parent_idx;
+	const char	*parent_name;
 };
 
 struct eqc_match_data {
@@ -273,7 +275,8 @@ static void eqc_probe_init_divs(struct device *dev, const struct eqc_match_data
 
 		if (IS_ERR(parent)) {
 			/* Parent is in early clk provider. */
-			parent_data.index = div->parent_idx;
+			parent_data.index = -1;
+			parent_data.name = div->parent_name;
 			parent_data.hw = NULL;
 		} else {
 			/* Avoid clock lookup when we already have the hw reference. */
@@ -305,8 +308,8 @@ static void eqc_probe_init_fixed_factors(struct device *dev,
 
 		if (IS_ERR(parent_hw)) {
 			/* Parent is in early clk provider. */
-			hw = clk_hw_register_fixed_factor_index(dev, ff->name,
-					ff->parent_idx, 0, ff->mult, ff->div);
+			hw = clk_hw_register_fixed_factor(dev, ff->name,
+					ff->parent_name, 0, ff->mult, ff->div);
 		} else {
 			/* Avoid clock lookup when we already have the hw reference. */
 			hw = clk_hw_register_fixed_factor_parent_hw(dev, ff->name,
@@ -487,35 +490,35 @@ static const struct eqc_fixed_factor eqc_eyeq5_early_fixed_factors[] = {
 
 static const struct eqc_fixed_factor eqc_eyeq5_fixed_factors[] = {
 	/* EQ5C_PLL_CPU children */
-	{ EQ5C_CPU_CPC,		"cpc",		1, 1,	EQ5C_CPU_SI_CSS0 },
-	{ EQ5C_CPU_CM,		"cm",		1, 1,	EQ5C_CPU_SI_CSS0 },
-	{ EQ5C_CPU_MEM,		"mem",		1, 1,	EQ5C_CPU_SI_CSS0 },
-	{ EQ5C_CPU_OCC_ISRAM,	"occ-isram",	1, 2,	EQ5C_PLL_CPU },
+	{ EQ5C_CPU_CPC,		"cpc",		1, 1,	EQ5C_CPU_SI_CSS0,	"si-css0" },
+	{ EQ5C_CPU_CM,		"cm",		1, 1,	EQ5C_CPU_SI_CSS0,	"si-css0" },
+	{ EQ5C_CPU_MEM,		"mem",		1, 1,	EQ5C_CPU_SI_CSS0,	"si-css0" },
+	{ EQ5C_CPU_OCC_ISRAM,	"occ-isram",	1, 2,	EQ5C_PLL_CPU,		"pll-cpu" },
 	{ EQ5C_CPU_ISRAM,	"isram",	1, 1,	EQ5C_CPU_OCC_ISRAM },
-	{ EQ5C_CPU_OCC_DBU,	"occ-dbu",	1, 10,	EQ5C_PLL_CPU },
+	{ EQ5C_CPU_OCC_DBU,	"occ-dbu",	1, 10,	EQ5C_PLL_CPU,		"pll-cpu" },
 	{ EQ5C_CPU_SI_DBU_TP,	"si-dbu-tp",	1, 1,	EQ5C_CPU_OCC_DBU },
 
 	/* EQ5C_PLL_VDI children */
-	{ EQ5C_VDI_OCC_VDI,	"occ-vdi",	1, 2,	EQ5C_PLL_VDI },
+	{ EQ5C_VDI_OCC_VDI,	"occ-vdi",	1, 2,	EQ5C_PLL_VDI,		"pll-vdi" },
 	{ EQ5C_VDI_VDI,		"vdi",		1, 1,	EQ5C_VDI_OCC_VDI },
-	{ EQ5C_VDI_OCC_CAN_SER,	"occ-can-ser",	1, 16,	EQ5C_PLL_VDI },
+	{ EQ5C_VDI_OCC_CAN_SER,	"occ-can-ser",	1, 16,	EQ5C_PLL_VDI,		"pll-vdi" },
 	{ EQ5C_VDI_CAN_SER,	"can-ser",	1, 1,	EQ5C_VDI_OCC_CAN_SER },
-	{ EQ5C_VDI_I2C_SER,	"i2c-ser",	1, 20,	EQ5C_PLL_VDI },
+	{ EQ5C_VDI_I2C_SER,	"i2c-ser",	1, 20,	EQ5C_PLL_VDI,		"pll-vdi" },
 
 	/* EQ5C_PLL_PER children */
-	{ EQ5C_PER_PERIPH,	"periph",	1, 1,	EQ5C_PER_OCC },
-	{ EQ5C_PER_CAN,		"can",		1, 1,	EQ5C_PER_OCC },
-	{ EQ5C_PER_SPI,		"spi",		1, 1,	EQ5C_PER_OCC },
-	{ EQ5C_PER_I2C,		"i2c",		1, 1,	EQ5C_PER_OCC },
-	{ EQ5C_PER_TIMER,	"timer",	1, 1,	EQ5C_PER_OCC },
-	{ EQ5C_PER_GPIO,	"gpio",		1, 1,	EQ5C_PER_OCC },
-	{ EQ5C_PER_EMMC,	"emmc-sys",	1, 10,	EQ5C_PLL_PER },
-	{ EQ5C_PER_CCF,		"ccf-ctrl",	1, 4,	EQ5C_PLL_PER },
-	{ EQ5C_PER_OCC_MJPEG,	"occ-mjpeg",	1, 2,	EQ5C_PLL_PER },
+	{ EQ5C_PER_PERIPH,	"periph",	1, 1,	EQ5C_PER_OCC,		 "occ-periph" },
+	{ EQ5C_PER_CAN,		"can",		1, 1,	EQ5C_PER_OCC,		 "occ-periph" },
+	{ EQ5C_PER_SPI,		"spi",		1, 1,	EQ5C_PER_OCC,		 "occ-periph" },
+	{ EQ5C_PER_I2C,		"i2c",		1, 1,	EQ5C_PER_OCC,		 "occ-periph" },
+	{ EQ5C_PER_TIMER,	"timer",	1, 1,	EQ5C_PER_OCC,		 "occ-periph" },
+	{ EQ5C_PER_GPIO,	"gpio",		1, 1,	EQ5C_PER_OCC,		 "occ-periph" },
+	{ EQ5C_PER_EMMC,	"emmc-sys",	1, 10,	EQ5C_PLL_PER,		 "pll-per" },
+	{ EQ5C_PER_CCF,		"ccf-ctrl",	1, 4,	EQ5C_PLL_PER,		 "pll-per" },
+	{ EQ5C_PER_OCC_MJPEG,	"occ-mjpeg",	1, 2,	EQ5C_PLL_PER,		 "pll-per" },
 	{ EQ5C_PER_HSM,		"hsm",		1, 1,	EQ5C_PER_OCC_MJPEG },
 	{ EQ5C_PER_MJPEG,	"mjpeg",	1, 1,	EQ5C_PER_OCC_MJPEG },
-	{ EQ5C_PER_FCMU_A,	"fcmu-a",	1, 20,	EQ5C_PLL_PER },
-	{ EQ5C_PER_OCC_PCI,	"occ-pci-sys",	1, 8,	EQ5C_PLL_PER },
+	{ EQ5C_PER_FCMU_A,	"fcmu-a",	1, 20,	EQ5C_PLL_PER,		 "pll-per" },
+	{ EQ5C_PER_OCC_PCI,	"occ-pci-sys",	1, 8,	EQ5C_PLL_PER,		 "pll-per" },
 };
 
 static const struct eqc_div eqc_eyeq5_divs[] = {
@@ -523,6 +526,7 @@ static const struct eqc_div eqc_eyeq5_divs[] = {
 		.index = EQ5C_DIV_OSPI,
 		.name = "div-ospi",
 		.parent_idx = EQ5C_PLL_PER,
+		.parent_name = "pll-per",
 		.reg = 0x11C,
 		.shift = 0,
 		.width = 4,

-- 
2.51.0

[PATCH 13/19] clk: eyeq: prefix the PLL registers with the PLL type

[Benoît Monin]

Rename the PLL registers to make room for other PLL types that are
present in the eyeQ7H.

We only prefix the register with the PLL type (FRACG), no other change.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 50 +++++++++++++++++++++++++-------------------------
 1 file changed, 25 insertions(+), 25 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index a0581016100c7367efb373a3fb3b7c6d51b49912..63093a3099261e6798a6752651d25efa1b3e7592 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -47,28 +47,28 @@
 #include <dt-bindings/clock/mobileye,eyeq-clk.h>
 
 /* In frac mode, it enables fractional noise canceling DAC. Else, no function. */
-#define PCSR0_DAC_EN			BIT(0)
+#define FRACG_PCSR0_DAC_EN			BIT(0)
 /* Fractional or integer mode */
-#define PCSR0_DSM_EN			BIT(1)
-#define PCSR0_PLL_EN			BIT(2)
+#define FRACG_PCSR0_DSM_EN			BIT(1)
+#define FRACG_PCSR0_PLL_EN			BIT(2)
 /* All clocks output held at 0 */
-#define PCSR0_FOUTPOSTDIV_EN		BIT(3)
-#define PCSR0_POST_DIV1			GENMASK(6, 4)
-#define PCSR0_POST_DIV2			GENMASK(9, 7)
-#define PCSR0_REF_DIV			GENMASK(15, 10)
-#define PCSR0_INTIN			GENMASK(27, 16)
-#define PCSR0_BYPASS			BIT(28)
+#define FRACG_PCSR0_FOUTPOSTDIV_EN		BIT(3)
+#define FRACG_PCSR0_POST_DIV1			GENMASK(6, 4)
+#define FRACG_PCSR0_POST_DIV2			GENMASK(9, 7)
+#define FRACG_PCSR0_REF_DIV			GENMASK(15, 10)
+#define FRACG_PCSR0_INTIN			GENMASK(27, 16)
+#define FRACG_PCSR0_BYPASS			BIT(28)
 /* Bits 30..29 are reserved */
-#define PCSR0_PLL_LOCKED		BIT(31)
+#define FRACG_PCSR0_PLL_LOCKED			BIT(31)
 
-#define PCSR1_RESET			BIT(0)
-#define PCSR1_SSGC_DIV			GENMASK(4, 1)
+#define FRACG_PCSR1_RESET			BIT(0)
+#define FRACG_PCSR1_SSGC_DIV			GENMASK(4, 1)
 /* Spread amplitude (% = 0.1 * SPREAD[4:0]) */
-#define PCSR1_SPREAD			GENMASK(9, 5)
-#define PCSR1_DIS_SSCG			BIT(10)
+#define FRACG_PCSR1_SPREAD			GENMASK(9, 5)
+#define FRACG_PCSR1_DIS_SSCG			BIT(10)
 /* Down-spread or center-spread */
-#define PCSR1_DOWN_SPREAD		BIT(11)
-#define PCSR1_FRAC_IN			GENMASK(31, 12)
+#define FRACG_PCSR1_DOWN_SPREAD			BIT(11)
+#define FRACG_PCSR1_FRAC_IN			GENMASK(31, 12)
 
 struct eqc_pll {
 	unsigned int	index;
@@ -167,29 +167,29 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
 {
 	u32 spread;
 
-	if (r0 & PCSR0_BYPASS) {
+	if (r0 & FRACG_PCSR0_BYPASS) {
 		*mult = 1;
 		*div = 1;
 		*acc = 0;
 		return 0;
 	}
 
-	if (!(r0 & PCSR0_PLL_LOCKED))
+	if (!(r0 & FRACG_PCSR0_PLL_LOCKED))
 		return -EINVAL;
 
-	*mult = FIELD_GET(PCSR0_INTIN, r0);
-	*div = FIELD_GET(PCSR0_REF_DIV, r0);
+	*mult = FIELD_GET(FRACG_PCSR0_INTIN, r0);
+	*div = FIELD_GET(FRACG_PCSR0_REF_DIV, r0);
 
 	/* Fractional mode, in 2^20 (0x100000) parts. */
-	if (r0 & PCSR0_DSM_EN) {
+	if (r0 & FRACG_PCSR0_DSM_EN) {
 		*div *= (1ULL << 20);
-		*mult = *mult * (1ULL << 20) + FIELD_GET(PCSR1_FRAC_IN, r1);
+		*mult = *mult * (1ULL << 20) + FIELD_GET(FRACG_PCSR1_FRAC_IN, r1);
 	}
 
 	if (!*mult || !*div)
 		return -EINVAL;
 
-	if (r1 & (PCSR1_RESET | PCSR1_DIS_SSCG)) {
+	if (r1 & (FRACG_PCSR1_RESET | FRACG_PCSR1_DIS_SSCG)) {
 		*acc = 0;
 		return 0;
 	}
@@ -204,10 +204,10 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
 	 *   with acc in parts per billion and,
 	 *        spread in parts per thousand.
 	 */
-	spread = FIELD_GET(PCSR1_SPREAD, r1);
+	spread = FIELD_GET(FRACG_PCSR1_SPREAD, r1);
 	*acc = spread * 500000;
 
-	if (r1 & PCSR1_DOWN_SPREAD) {
+	if (r1 & FRACG_PCSR1_DOWN_SPREAD) {
 		/*
 		 * Downspreading: the central frequency is half a
 		 * spread lower.

-- 
2.51.0

[PATCH 14/19] clk: eyeq: rename the reg64 field of eqc_pll

[Benoît Monin]

Not all PLL types need a 64 bits access, make the field name more
generic by renaming it to reg.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 64 +++++++++++++++++++++++++-------------------------
 1 file changed, 32 insertions(+), 32 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 63093a3099261e6798a6752651d25efa1b3e7592..0379fe7593453e72dd8983c743561caa385a3fbd 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -73,7 +73,7 @@
 struct eqc_pll {
 	unsigned int	index;
 	const char	*name;
-	unsigned int	reg64;
+	unsigned int	reg;
 };
 
 /*
@@ -239,7 +239,7 @@ static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data
 	for (i = 0; i < data->pll_count; i++) {
 		pll = &data->plls[i];
 
-		val = readq(base + pll->reg64);
+		val = readq(base + pll->reg);
 		r0 = val;
 		r1 = val >> 32;
 
@@ -422,19 +422,19 @@ static int eqc_probe(struct platform_device *pdev)
 
 /* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */
 static const struct eqc_pll eqc_eyeq5_early_plls[] = {
-	{ .index = EQ5C_PLL_CPU, .name = "pll-cpu",  .reg64 = 0x02C },
-	{ .index = EQ5C_PLL_PER, .name = "pll-per",  .reg64 = 0x05C },
+	{ .index = EQ5C_PLL_CPU, .name = "pll-cpu",  .reg = 0x02C },
+	{ .index = EQ5C_PLL_PER, .name = "pll-per",  .reg = 0x05C },
 };
 
 static const struct eqc_pll eqc_eyeq5_plls[] = {
-	{ .index = EQ5C_PLL_VMP,  .name = "pll-vmp",  .reg64 = 0x034 },
-	{ .index = EQ5C_PLL_PMA,  .name = "pll-pma",  .reg64 = 0x03C },
-	{ .index = EQ5C_PLL_VDI,  .name = "pll-vdi",  .reg64 = 0x044 },
-	{ .index = EQ5C_PLL_DDR0, .name = "pll-ddr0", .reg64 = 0x04C },
-	{ .index = EQ5C_PLL_PCI,  .name = "pll-pci",  .reg64 = 0x054 },
-	{ .index = EQ5C_PLL_PMAC, .name = "pll-pmac", .reg64 = 0x064 },
-	{ .index = EQ5C_PLL_MPC,  .name = "pll-mpc",  .reg64 = 0x06C },
-	{ .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg64 = 0x074 },
+	{ .index = EQ5C_PLL_VMP,  .name = "pll-vmp",  .reg = 0x034 },
+	{ .index = EQ5C_PLL_PMA,  .name = "pll-pma",  .reg = 0x03C },
+	{ .index = EQ5C_PLL_VDI,  .name = "pll-vdi",  .reg = 0x044 },
+	{ .index = EQ5C_PLL_DDR0, .name = "pll-ddr0", .reg = 0x04C },
+	{ .index = EQ5C_PLL_PCI,  .name = "pll-pci",  .reg = 0x054 },
+	{ .index = EQ5C_PLL_PMAC, .name = "pll-pmac", .reg = 0x064 },
+	{ .index = EQ5C_PLL_MPC,  .name = "pll-mpc",  .reg = 0x06C },
+	{ .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg = 0x074 },
 };
 
 enum {
@@ -562,10 +562,10 @@ static const struct eqc_match_data eqc_eyeq5_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6l_plls[] = {
-	{ .index = EQ6LC_PLL_DDR, .name = "pll-ddr", .reg64 = 0x02C },
-	{ .index = EQ6LC_PLL_CPU, .name = "pll-cpu", .reg64 = 0x034 }, /* also acc */
-	{ .index = EQ6LC_PLL_PER, .name = "pll-per", .reg64 = 0x03C },
-	{ .index = EQ6LC_PLL_VDI, .name = "pll-vdi", .reg64 = 0x044 },
+	{ .index = EQ6LC_PLL_DDR, .name = "pll-ddr", .reg = 0x02C },
+	{ .index = EQ6LC_PLL_CPU, .name = "pll-cpu", .reg = 0x034 }, /* also acc */
+	{ .index = EQ6LC_PLL_PER, .name = "pll-per", .reg = 0x03C },
+	{ .index = EQ6LC_PLL_VDI, .name = "pll-vdi", .reg = 0x044 },
 };
 
 static const struct eqc_match_data eqc_eyeq6l_match_data = {
@@ -580,7 +580,7 @@ static const struct eqc_match_data eqc_eyeq6h_west_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6h_east_plls[] = {
-	{ .index = 0, .name = "pll-east", .reg64 = 0x074 },
+	{ .index = 0, .name = "pll-east", .reg = 0x074 },
 };
 
 static const struct eqc_match_data eqc_eyeq6h_east_match_data = {
@@ -591,10 +591,10 @@ static const struct eqc_match_data eqc_eyeq6h_east_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6h_south_plls[] = {
-	{ .index = EQ6HC_SOUTH_PLL_VDI,  .name = "pll-vdi",  .reg64 = 0x000 },
-	{ .index = EQ6HC_SOUTH_PLL_PCIE, .name = "pll-pcie", .reg64 = 0x008 },
-	{ .index = EQ6HC_SOUTH_PLL_PER,  .name = "pll-per",  .reg64 = 0x010 },
-	{ .index = EQ6HC_SOUTH_PLL_ISP,  .name = "pll-isp",  .reg64 = 0x018 },
+	{ .index = EQ6HC_SOUTH_PLL_VDI,  .name = "pll-vdi",  .reg = 0x000 },
+	{ .index = EQ6HC_SOUTH_PLL_PCIE, .name = "pll-pcie", .reg = 0x008 },
+	{ .index = EQ6HC_SOUTH_PLL_PER,  .name = "pll-per",  .reg = 0x010 },
+	{ .index = EQ6HC_SOUTH_PLL_ISP,  .name = "pll-isp",  .reg = 0x018 },
 };
 
 static const struct eqc_div eqc_eyeq6h_south_divs[] = {
@@ -641,7 +641,7 @@ static const struct eqc_match_data eqc_eyeq6h_south_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6h_ddr0_plls[] = {
-	{ .index = 0, .name = "pll-ddr0", .reg64 = 0x074 },
+	{ .index = 0, .name = "pll-ddr0", .reg = 0x074 },
 };
 
 static const struct eqc_match_data eqc_eyeq6h_ddr0_match_data = {
@@ -650,7 +650,7 @@ static const struct eqc_match_data eqc_eyeq6h_ddr0_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6h_ddr1_plls[] = {
-	{ .index = 0, .name = "pll-ddr1", .reg64 = 0x074 },
+	{ .index = 0, .name = "pll-ddr1", .reg = 0x074 },
 };
 
 static const struct eqc_match_data eqc_eyeq6h_ddr1_match_data = {
@@ -659,11 +659,11 @@ static const struct eqc_match_data eqc_eyeq6h_ddr1_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6h_acc_plls[] = {
-	{ .index = EQ6HC_ACC_PLL_XNN, .name = "pll-xnn", .reg64 = 0x040 },
-	{ .index = EQ6HC_ACC_PLL_VMP, .name = "pll-vmp", .reg64 = 0x050 },
-	{ .index = EQ6HC_ACC_PLL_PMA, .name = "pll-pma", .reg64 = 0x05C },
-	{ .index = EQ6HC_ACC_PLL_MPC, .name = "pll-mpc", .reg64 = 0x068 },
-	{ .index = EQ6HC_ACC_PLL_NOC, .name = "pll-noc", .reg64 = 0x070 },
+	{ .index = EQ6HC_ACC_PLL_XNN, .name = "pll-xnn", .reg = 0x040 },
+	{ .index = EQ6HC_ACC_PLL_VMP, .name = "pll-vmp", .reg = 0x050 },
+	{ .index = EQ6HC_ACC_PLL_PMA, .name = "pll-pma", .reg = 0x05C },
+	{ .index = EQ6HC_ACC_PLL_MPC, .name = "pll-mpc", .reg = 0x068 },
+	{ .index = EQ6HC_ACC_PLL_NOC, .name = "pll-noc", .reg = 0x070 },
 };
 
 static const struct eqc_match_data eqc_eyeq6h_acc_match_data = {
@@ -697,7 +697,7 @@ builtin_platform_driver(eqc_driver);
 
 /* Required early for GIC timer. */
 static const struct eqc_pll eqc_eyeq6h_central_early_plls[] = {
-	{ .index = EQ6HC_CENTRAL_PLL_CPU, .name = "pll-cpu", .reg64 = 0x02C },
+	{ .index = EQ6HC_CENTRAL_PLL_CPU, .name = "pll-cpu", .reg = 0x02C },
 };
 
 static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factors[] = {
@@ -714,7 +714,7 @@ static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __i
 
 /* Required early for UART. */
 static const struct eqc_pll eqc_eyeq6h_west_early_plls[] = {
-	{ .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg64 = 0x074 },
+	{ .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg = 0x074 },
 };
 
 static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[] = {
@@ -758,7 +758,7 @@ static void __init eqc_early_init(struct device_node *np,
 	for (i = 0; i < clk_count; i++)
 		cells->hws[i] = ERR_PTR(-EPROBE_DEFER);
 
-	/* Offsets (reg64) of early PLLs are relative to OLB block. */
+	/* Offsets (reg) of early PLLs are relative to OLB block. */
 	base = of_iomap(np, 0);
 	if (!base) {
 		ret = -ENODEV;
@@ -772,7 +772,7 @@ static void __init eqc_early_init(struct device_node *np,
 		u32 r0, r1;
 		u64 val;
 
-		val = readq(base + pll->reg64);
+		val = readq(base + pll->reg);
 		r0 = val;
 		r1 = val >> 32;
 

-- 
2.51.0

[PATCH 15/19] clk: eyeq: add a type for the PLL

[Benoît Monin]

Add a type field to the eqc_pll structure and parse the registers of
the PLL depending on its type. This makes room for adding new PLL types
found in the eyeQ7H OLB.

Each PLL type now comes with its own registers parsing function that is
called based on the type.

For now, only the FRACG type is implemented.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 104 +++++++++++++++++++++++++++----------------------
 1 file changed, 57 insertions(+), 47 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 0379fe7593453e72dd8983c743561caa385a3fbd..07a205fefd93eed8f9c2c6b88fbf5b8b6a39a92c 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -70,10 +70,15 @@
 #define FRACG_PCSR1_DOWN_SPREAD			BIT(11)
 #define FRACG_PCSR1_FRAC_IN			GENMASK(31, 12)
 
+enum eqc_pll_type {
+	EQC_PLL_FRACG,
+};
+
 struct eqc_pll {
-	unsigned int	index;
-	const char	*name;
-	unsigned int	reg;
+	unsigned int		index;
+	const char		*name;
+	unsigned int		reg;
+	enum eqc_pll_type	type;
 };
 
 /*
@@ -162,11 +167,17 @@ static void eqc_pll_downshift_factors(unsigned long *mult, unsigned long *div)
 	*div >>= shift;
 }
 
-static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
-				   unsigned long *div, unsigned long *acc)
+static int eqc_pll_parse_fracg(void __iomem *base, unsigned long *mult,
+			       unsigned long *div, unsigned long *acc)
 {
+	u64 val;
+	u32 r0, r1;
 	u32 spread;
 
+	val = readq(base);
+	r0 = val;
+	r1 = val >> 32;
+
 	if (r0 & FRACG_PCSR0_BYPASS) {
 		*mult = 1;
 		*div = 1;
@@ -225,6 +236,16 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
 	return 0;
 }
 
+static int eqc_parse_one_pll(void __iomem *base, enum eqc_pll_type type, unsigned long *mult,
+			     unsigned long *div, unsigned long *acc)
+{
+	switch (type) {
+	case EQC_PLL_FRACG:
+		return eqc_pll_parse_fracg(base, mult, div, acc);
+	}
+	return -EINVAL;
+}
+
 static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data *data,
 				void __iomem *base, struct clk_hw_onecell_data *cells)
 {
@@ -232,18 +253,12 @@ static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data
 	const struct eqc_pll *pll;
 	struct clk_hw *hw;
 	unsigned int i;
-	u32 r0, r1;
-	u64 val;
 	int ret;
 
 	for (i = 0; i < data->pll_count; i++) {
 		pll = &data->plls[i];
 
-		val = readq(base + pll->reg);
-		r0 = val;
-		r1 = val >> 32;
-
-		ret = eqc_pll_parse_registers(r0, r1, &mult, &div, &acc);
+		ret = eqc_parse_one_pll(base + pll->reg, pll->type, &mult, &div, &acc);
 		if (ret) {
 			dev_warn(dev, "failed parsing state of %s\n", pll->name);
 			cells->hws[pll->index] = ERR_PTR(ret);
@@ -422,19 +437,19 @@ static int eqc_probe(struct platform_device *pdev)
 
 /* Required early for GIC timer (pll-cpu) and UARTs (pll-per). */
 static const struct eqc_pll eqc_eyeq5_early_plls[] = {
-	{ .index = EQ5C_PLL_CPU, .name = "pll-cpu",  .reg = 0x02C },
-	{ .index = EQ5C_PLL_PER, .name = "pll-per",  .reg = 0x05C },
+	{ .index = EQ5C_PLL_CPU, .name = "pll-cpu",  .reg = 0x02C, .type = EQC_PLL_FRACG },
+	{ .index = EQ5C_PLL_PER, .name = "pll-per",  .reg = 0x05C, .type = EQC_PLL_FRACG },
 };
 
 static const struct eqc_pll eqc_eyeq5_plls[] = {
-	{ .index = EQ5C_PLL_VMP,  .name = "pll-vmp",  .reg = 0x034 },
-	{ .index = EQ5C_PLL_PMA,  .name = "pll-pma",  .reg = 0x03C },
-	{ .index = EQ5C_PLL_VDI,  .name = "pll-vdi",  .reg = 0x044 },
-	{ .index = EQ5C_PLL_DDR0, .name = "pll-ddr0", .reg = 0x04C },
-	{ .index = EQ5C_PLL_PCI,  .name = "pll-pci",  .reg = 0x054 },
-	{ .index = EQ5C_PLL_PMAC, .name = "pll-pmac", .reg = 0x064 },
-	{ .index = EQ5C_PLL_MPC,  .name = "pll-mpc",  .reg = 0x06C },
-	{ .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg = 0x074 },
+	{ .index = EQ5C_PLL_VMP,  .name = "pll-vmp",  .reg = 0x034, .type = EQC_PLL_FRACG },
+	{ .index = EQ5C_PLL_PMA,  .name = "pll-pma",  .reg = 0x03C, .type = EQC_PLL_FRACG },
+	{ .index = EQ5C_PLL_VDI,  .name = "pll-vdi",  .reg = 0x044, .type = EQC_PLL_FRACG },
+	{ .index = EQ5C_PLL_DDR0, .name = "pll-ddr0", .reg = 0x04C, .type = EQC_PLL_FRACG },
+	{ .index = EQ5C_PLL_PCI,  .name = "pll-pci",  .reg = 0x054, .type = EQC_PLL_FRACG },
+	{ .index = EQ5C_PLL_PMAC, .name = "pll-pmac", .reg = 0x064, .type = EQC_PLL_FRACG },
+	{ .index = EQ5C_PLL_MPC,  .name = "pll-mpc",  .reg = 0x06C, .type = EQC_PLL_FRACG },
+	{ .index = EQ5C_PLL_DDR1, .name = "pll-ddr1", .reg = 0x074, .type = EQC_PLL_FRACG },
 };
 
 enum {
@@ -562,10 +577,11 @@ static const struct eqc_match_data eqc_eyeq5_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6l_plls[] = {
-	{ .index = EQ6LC_PLL_DDR, .name = "pll-ddr", .reg = 0x02C },
-	{ .index = EQ6LC_PLL_CPU, .name = "pll-cpu", .reg = 0x034 }, /* also acc */
-	{ .index = EQ6LC_PLL_PER, .name = "pll-per", .reg = 0x03C },
-	{ .index = EQ6LC_PLL_VDI, .name = "pll-vdi", .reg = 0x044 },
+	{ .index = EQ6LC_PLL_DDR, .name = "pll-ddr", .reg = 0x02C, .type = EQC_PLL_FRACG },
+	/* pll-cpu also for acc */
+	{ .index = EQ6LC_PLL_CPU, .name = "pll-cpu", .reg = 0x034, .type = EQC_PLL_FRACG },
+	{ .index = EQ6LC_PLL_PER, .name = "pll-per", .reg = 0x03C, .type = EQC_PLL_FRACG },
+	{ .index = EQ6LC_PLL_VDI, .name = "pll-vdi", .reg = 0x044, .type = EQC_PLL_FRACG },
 };
 
 static const struct eqc_match_data eqc_eyeq6l_match_data = {
@@ -580,7 +596,7 @@ static const struct eqc_match_data eqc_eyeq6h_west_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6h_east_plls[] = {
-	{ .index = 0, .name = "pll-east", .reg = 0x074 },
+	{ .index = 0, .name = "pll-east", .reg = 0x074, .type = EQC_PLL_FRACG },
 };
 
 static const struct eqc_match_data eqc_eyeq6h_east_match_data = {
@@ -591,10 +607,10 @@ static const struct eqc_match_data eqc_eyeq6h_east_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6h_south_plls[] = {
-	{ .index = EQ6HC_SOUTH_PLL_VDI,  .name = "pll-vdi",  .reg = 0x000 },
-	{ .index = EQ6HC_SOUTH_PLL_PCIE, .name = "pll-pcie", .reg = 0x008 },
-	{ .index = EQ6HC_SOUTH_PLL_PER,  .name = "pll-per",  .reg = 0x010 },
-	{ .index = EQ6HC_SOUTH_PLL_ISP,  .name = "pll-isp",  .reg = 0x018 },
+	{ .index = EQ6HC_SOUTH_PLL_VDI,  .name = "pll-vdi",  .reg = 0x000, .type = EQC_PLL_FRACG },
+	{ .index = EQ6HC_SOUTH_PLL_PCIE, .name = "pll-pcie", .reg = 0x008, .type = EQC_PLL_FRACG },
+	{ .index = EQ6HC_SOUTH_PLL_PER,  .name = "pll-per",  .reg = 0x010, .type = EQC_PLL_FRACG },
+	{ .index = EQ6HC_SOUTH_PLL_ISP,  .name = "pll-isp",  .reg = 0x018, .type = EQC_PLL_FRACG },
 };
 
 static const struct eqc_div eqc_eyeq6h_south_divs[] = {
@@ -641,7 +657,7 @@ static const struct eqc_match_data eqc_eyeq6h_south_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6h_ddr0_plls[] = {
-	{ .index = 0, .name = "pll-ddr0", .reg = 0x074 },
+	{ .index = 0, .name = "pll-ddr0", .reg = 0x074, .type = EQC_PLL_FRACG },
 };
 
 static const struct eqc_match_data eqc_eyeq6h_ddr0_match_data = {
@@ -650,7 +666,7 @@ static const struct eqc_match_data eqc_eyeq6h_ddr0_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6h_ddr1_plls[] = {
-	{ .index = 0, .name = "pll-ddr1", .reg = 0x074 },
+	{ .index = 0, .name = "pll-ddr1", .reg = 0x074, .type = EQC_PLL_FRACG },
 };
 
 static const struct eqc_match_data eqc_eyeq6h_ddr1_match_data = {
@@ -659,11 +675,11 @@ static const struct eqc_match_data eqc_eyeq6h_ddr1_match_data = {
 };
 
 static const struct eqc_pll eqc_eyeq6h_acc_plls[] = {
-	{ .index = EQ6HC_ACC_PLL_XNN, .name = "pll-xnn", .reg = 0x040 },
-	{ .index = EQ6HC_ACC_PLL_VMP, .name = "pll-vmp", .reg = 0x050 },
-	{ .index = EQ6HC_ACC_PLL_PMA, .name = "pll-pma", .reg = 0x05C },
-	{ .index = EQ6HC_ACC_PLL_MPC, .name = "pll-mpc", .reg = 0x068 },
-	{ .index = EQ6HC_ACC_PLL_NOC, .name = "pll-noc", .reg = 0x070 },
+	{ .index = EQ6HC_ACC_PLL_XNN, .name = "pll-xnn", .reg = 0x040, .type = EQC_PLL_FRACG },
+	{ .index = EQ6HC_ACC_PLL_VMP, .name = "pll-vmp", .reg = 0x050, .type = EQC_PLL_FRACG },
+	{ .index = EQ6HC_ACC_PLL_PMA, .name = "pll-pma", .reg = 0x05C, .type = EQC_PLL_FRACG },
+	{ .index = EQ6HC_ACC_PLL_MPC, .name = "pll-mpc", .reg = 0x068, .type = EQC_PLL_FRACG },
+	{ .index = EQ6HC_ACC_PLL_NOC, .name = "pll-noc", .reg = 0x070, .type = EQC_PLL_FRACG },
 };
 
 static const struct eqc_match_data eqc_eyeq6h_acc_match_data = {
@@ -697,7 +713,7 @@ builtin_platform_driver(eqc_driver);
 
 /* Required early for GIC timer. */
 static const struct eqc_pll eqc_eyeq6h_central_early_plls[] = {
-	{ .index = EQ6HC_CENTRAL_PLL_CPU, .name = "pll-cpu", .reg = 0x02C },
+	{ .index = EQ6HC_CENTRAL_PLL_CPU, .name = "pll-cpu", .reg = 0x02C, .type = EQC_PLL_FRACG },
 };
 
 static const struct eqc_fixed_factor eqc_eyeq6h_central_early_fixed_factors[] = {
@@ -714,7 +730,7 @@ static const struct eqc_early_match_data eqc_eyeq6h_central_early_match_data __i
 
 /* Required early for UART. */
 static const struct eqc_pll eqc_eyeq6h_west_early_plls[] = {
-	{ .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg = 0x074 },
+	{ .index = EQ6HC_WEST_PLL_PER, .name = "pll-west", .reg = 0x074, .type = EQC_PLL_FRACG },
 };
 
 static const struct eqc_fixed_factor eqc_eyeq6h_west_early_fixed_factors[] = {
@@ -769,14 +785,8 @@ static void __init eqc_early_init(struct device_node *np,
 		const struct eqc_pll *pll = &early_data->early_plls[i];
 		unsigned long mult, div, acc;
 		struct clk_hw *hw;
-		u32 r0, r1;
-		u64 val;
 
-		val = readq(base + pll->reg);
-		r0 = val;
-		r1 = val >> 32;
-
-		ret = eqc_pll_parse_registers(r0, r1, &mult, &div, &acc);
+		ret = eqc_parse_one_pll(base + pll->reg, pll->type, &mult, &div, &acc);
 		if (ret) {
 			pr_err("failed parsing state of %s\n", pll->name);
 			goto err;

-- 
2.51.0

[PATCH 16/19] clk: eyeq: add two PLL types

[Benoît Monin]

Add the handling of the two types of PLL found in the eyeQ7H OLB.

The JFRACR PLL have similar properties as the FRACG PLL, but its
configuration is spread on three registers instead of two.

The AINTP PLL does not support spread spectrum and uses a single
register.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 117 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 117 insertions(+)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 07a205fefd93eed8f9c2c6b88fbf5b8b6a39a92c..cf745671d86a5fc770ec3599561eb3468e13bd58 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -70,8 +70,44 @@
 #define FRACG_PCSR1_DOWN_SPREAD			BIT(11)
 #define FRACG_PCSR1_FRAC_IN			GENMASK(31, 12)
 
+#define JFRACR_PCSR0_BYPASS			BIT(0)
+#define JFRACR_PCSR0_PLL_EN			BIT(1)
+#define JFRACR_PCSR0_FOUTVCO_EN			BIT(2)
+#define JFRACR_PCSR0_FOUTPOSTDIV_EN		BIT(3)
+#define JFRACR_PCSR0_POST_DIV1			GENMASK(6, 4)
+#define JFRACR_PCSR0_POST_DIV2			GENMASK(9, 7)
+#define JFRACR_PCSR0_REF_DIV			GENMASK(15, 10)
+#define JFRACR_PCSR0_FB_DIV			GENMASK(27, 16)
+#define JFRACR_PCSR0_VCO_SEL			GENMASK(29, 28)
+#define JFRACR_PCSR0_PLL_LOCKED			GENMASK(31, 30)
+
+#define JFRACR_PCSR1_FRAC_IN			GENMASK(23, 0)
+#define JFRACR_PCSR1_FOUT4PHASE_EN		BIT(24)
+#define JFRACR_PCSR1_DAC_EN			BIT(25)
+#define JFRACR_PCSR1_DSM_EN			BIT(26)
+/* Bits 31..27 are reserved */
+#define JFRACR_PCSR2_RESET			BIT(0)
+#define JFRACR_PCSR2_DIS_SSCG			BIT(1)
+#define JFRACR_PCSR2_DOWN_SPREAD		BIT(2)
+#define JFRACR_PCSR2_SSGC_DIV			GENMASK(7, 4)
+#define JFRACR_PCSR2_SPREAD			GENMASK(12, 8)
+/* Bits 31..13 are reserved */
+
+#define AINTP_PCSR_BYPASS			BIT(0)
+#define AINTP_PCSR_PLL_EN			BIT(1)
+#define AINTP_PCSR_FOUTVCO_EN			BIT(2)
+#define AINTP_PCSR_FOUTPOSTDIV_EN		BIT(3)
+#define AINTP_PCSR_POST_DIV1			GENMASK(6, 4)
+#define AINTP_PCSR_POST_DIV2			GENMASK(9, 7)
+#define AINTP_PCSR_REF_DIV			GENMASK(15, 10)
+#define AINTP_PCSR_FB_DIV			GENMASK(27, 16)
+#define AINTP_PCSR_VCO_SEL			GENMASK(29, 28)
+#define AINTP_PCSR_PLL_LOCKED			GENMASK(31, 30)
+
 enum eqc_pll_type {
 	EQC_PLL_FRACG,
+	EQC_PLL_JFRACR,
+	EQC_PLL_AINTP,
 };
 
 struct eqc_pll {
@@ -236,12 +272,93 @@ static int eqc_pll_parse_fracg(void __iomem *base, unsigned long *mult,
 	return 0;
 }
 
+static int eqc_pll_parse_jfracr(void __iomem *base, unsigned long *mult,
+				unsigned long *div, unsigned long *acc)
+{
+	u64 val;
+	u32 r0, r1, r2;
+	u32 spread;
+
+	val = readq(base);
+	r0 = val;
+	r1 = val >> 32;
+	r2 = readl(base + 8);
+
+	if (r0 & JFRACR_PCSR0_BYPASS) {
+		*mult = 1;
+		*div = 1;
+		*acc = 0;
+		return 0;
+	}
+
+	if (!(r0 & JFRACR_PCSR0_PLL_LOCKED))
+		return -EINVAL;
+
+	*mult = FIELD_GET(JFRACR_PCSR0_FB_DIV, r0);
+	*div = FIELD_GET(JFRACR_PCSR0_REF_DIV, r0);
+
+	if (r1 & JFRACR_PCSR1_DSM_EN) {
+		*div *= (1ULL << 20);
+		*mult = *mult * (1ULL << 20) + FIELD_GET(JFRACR_PCSR1_FRAC_IN, r1);
+	}
+
+	if (!*mult || !*div)
+		return -EINVAL;
+
+	if (r2 & (JFRACR_PCSR2_RESET | JFRACR_PCSR2_DIS_SSCG)) {
+		*acc = 0;
+		return 0;
+	}
+
+	spread = FIELD_GET(JFRACR_PCSR2_SPREAD, r2);
+	*acc = spread * 500000;
+
+	if (r2 & JFRACR_PCSR2_DOWN_SPREAD) {
+		*mult *= 2000 - spread;
+		*div *= 2000;
+		eqc_pll_downshift_factors(mult, div);
+	}
+
+	return 0;
+}
+
+static int eqc_pll_parse_aintp(void __iomem *base, unsigned long *mult,
+			       unsigned long *div, unsigned long *acc)
+{
+	u32 r0;
+
+	/* no spread spectrum */
+	*acc = 0;
+
+	r0 = readl(base);
+	if (r0 & AINTP_PCSR_BYPASS) {
+		*mult = 1;
+		*div = 1;
+		return 0;
+	}
+
+	if (!(r0 & AINTP_PCSR_PLL_LOCKED))
+		return -EINVAL;
+
+	*mult = FIELD_GET(AINTP_PCSR_FB_DIV, r0);
+	*div = FIELD_GET(AINTP_PCSR_REF_DIV, r0);
+
+	if (!*mult || !*div)
+		return -EINVAL;
+
+	return 0;
+}
+
 static int eqc_parse_one_pll(void __iomem *base, enum eqc_pll_type type, unsigned long *mult,
 			     unsigned long *div, unsigned long *acc)
 {
 	switch (type) {
 	case EQC_PLL_FRACG:
 		return eqc_pll_parse_fracg(base, mult, div, acc);
+	case EQC_PLL_JFRACR:
+		return eqc_pll_parse_jfracr(base, mult, div, acc);
+	case EQC_PLL_AINTP:
+		return eqc_pll_parse_aintp(base, mult, div, acc);
 	}
 	return -EINVAL;
 }

-- 
2.51.0

[PATCH 17/19] clk: eyeq: add a parent field to the pll

[Benoît Monin]

Allow setting the parent of a pll. If NULL, use the same "ref" clock as
before. If non-NULL, the name is looked up in the "clock-names" passed
in the device tree and if found it is used as the fw_name, similar to
how "ref" was used previously.

If not found, the name is used as the parent_name when registering the
clock with clk_hw_register_fixed_factor_with_accuracy. This last case
is used to refer to a clock registered in early init and used by the
same OLB during probe while avoiding a dependency cycle.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 19 +++++++++++++++++--
 1 file changed, 17 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index cf745671d86a5fc770ec3599561eb3468e13bd58..a6260c38393776afab60e994c99008cfeecf6bc3 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -115,6 +115,7 @@ struct eqc_pll {
 	const char		*name;
 	unsigned int		reg;
 	enum eqc_pll_type	type;
+	const char		*parent_name;
 };
 
 /*
@@ -366,8 +367,10 @@ static int eqc_parse_one_pll(void __iomem *base, enum eqc_pll_type type, unsigne
 static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data *data,
 				void __iomem *base, struct clk_hw_onecell_data *cells)
 {
+	struct device_node *np = dev->of_node;
 	unsigned long mult, div, acc;
 	const struct eqc_pll *pll;
+	const char *fw_name;
 	struct clk_hw *hw;
 	unsigned int i;
 	int ret;
@@ -382,8 +385,20 @@ static void eqc_probe_init_plls(struct device *dev, const struct eqc_match_data
 			continue;
 		}
 
-		hw = clk_hw_register_fixed_factor_with_accuracy_fwname(dev,
-				dev->of_node, pll->name, "ref", 0, mult, div, acc);
+		if (!pll->parent_name)
+			fw_name = "ref";
+		else if (of_property_match_string(np, "clock-names", pll->parent_name) >= 0)
+			fw_name = pll->parent_name;
+		else
+			fw_name = NULL;
+
+		if (fw_name)
+			hw = clk_hw_register_fixed_factor_with_accuracy_fwname(dev,
+					np, pll->name, fw_name, 0, mult, div, acc);
+		else
+			hw = clk_hw_register_fixed_factor_with_accuracy(dev,
+					pll->name, pll->parent_name, 0, mult, div, acc);
+
 		cells->hws[pll->index] = hw;
 		if (IS_ERR(hw))
 			dev_warn(dev, "failed registering %s: %pe\n", pll->name, hw);

-- 
2.51.0

[PATCH 18/19] clk: eyeq: add an optional clk_div_table to divider

[Benoît Monin]

The new type of divider in eyeQ7H OLB are table-based, use it if
present. Make sure we don't pass CLK_DIVIDER_EVEN_INTEGERS in the flags
when registerting a table based divider as it has priority over the
table.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 21 ++++++++++++---------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index a6260c38393776afab60e994c99008cfeecf6bc3..8d5e194215e9d3d13b334a5ebf004499050e84b9 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -119,17 +119,20 @@ struct eqc_pll {
 };
 
 /*
- * Divider clock. Divider is 2*(v+1), with v the register value.
+ * Divider clock.
+ * If the table is NULL, divider is 2*(v+1), with v the register value.
  * Min divider is 2, max is 2*(2^width).
+ * Otherwise the divider values are looked up in the table.
  */
 struct eqc_div {
-	unsigned int	index;
-	const char	*name;
-	unsigned int	parent_idx;
-	const char	*parent_name;
-	unsigned int	reg;
-	u8		shift;
-	u8		width;
+	unsigned int			index;
+	const char			*name;
+	unsigned int			parent_idx;
+	const char			*parent_name;
+	unsigned int			reg;
+	u8				shift;
+	u8				width;
+	const struct clk_div_table	*table;
 };
 
 struct eqc_fixed_factor {
@@ -433,7 +436,7 @@ static void eqc_probe_init_divs(struct device *dev, const struct eqc_match_data
 
 		hw = clk_hw_register_divider_table_parent_data(dev, div->name,
 				&parent_data, 0, reg, div->shift, div->width,
-				CLK_DIVIDER_EVEN_INTEGERS, NULL, NULL);
+				div->table ? 0 : CLK_DIVIDER_EVEN_INTEGERS, div->table, NULL);
 		cells->hws[div->index] = hw;
 		if (IS_ERR(hw))
 			dev_warn(dev, "failed registering %s: %pe\n",

-- 
2.51.0

[PATCH 19/19] clk: eyeq: add eyeQ7H compatibles

[Benoît Monin]

Add the entries for the 14 Other Logic Blocks found in the eyeQ7H SoC. The
clock tree is more complex than the previous generation of SoC, as some
OLB depend on the clock output of other OLB instead of all referring to
the main oscillator.

The OLB south, east and west generate those reference clocks used by
other blocks. They also use the reference clock internally. To avoid
creating a reference loop, we register those reference clocks early then
refer to them at probe time. This is the same approach that is used for
the clocks of the eyeQ5 OLB. The reference clock provided by OLB south
is named "ref_100p0", "ref_106p6_e" by OLB east and "ref_106p6_w" by
OLB west.

For the OLB with a single parent clock, We use the same logic as the
blocks found in previous SoC and refer to it with the implied name
"ref".

The OLB with two parent clocks use the reference clock names provided
by the OLB south, east and west and the main oscillator as "ref".

The reset controllers found is 11 of the OLB are declared as auxiliary
device attached to the clock device.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 495 +++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 495 insertions(+)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 8d5e194215e9d3d13b334a5ebf004499050e84b9..b9437003024fd0766fb1bd5d3e4916263f9cc854 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -824,6 +824,464 @@ static const struct eqc_match_data eqc_eyeq6h_acc_match_data = {
 	.reset_auxdev_name = "reset_acc",
 };
 
+/* Required early as reference for other PLL in OLB south */
+static const struct eqc_pll eqc_eyeq7h_south_early_plls[] = {
+	{ EQ7HC_SOUTH_PLL_100P0, "pll-100p0", 0x40, EQC_PLL_JFRACR },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_south_early_fixed_factors[] = {
+	{ EQ7HC_SOUTH_DIV_REF_100P0, "ref_100p0", 1, 48, EQ7HC_SOUTH_PLL_100P0 },
+};
+
+static const struct eqc_pll eqc_eyeq7h_south_plls[] = {
+	//{index, name, reg, type, parent}
+	{ EQ7HC_SOUTH_PLL_XSPI, "pll-xspi",  0x10, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_SOUTH_PLL_VDIO, "pll-vdio",  0x18, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_SOUTH_PLL_PER,  "pll-per-s", 0x20, EQC_PLL_AINTP, "ref_100p0" },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_south_fixed_factors[] = {
+	{ EQ7HC_SOUTH_DIV_VDO_DSI_SYS,    "vdo_dsi_sys",      1, 9,   EQ7HC_SOUTH_PLL_100P0,
+	  "pll-100p0" },
+	{ EQ7HC_SOUTH_DIV_PMA_CMN_REF,    "pma_cmn_ref",      1, 48,  EQ7HC_SOUTH_PLL_100P0,
+	  "pll-100p0" },
+	{ EQ7HC_SOUTH_DIV_REF_UFS,        "ref_ufs",          1, 250, EQ7HC_SOUTH_PLL_100P0,
+	  "pll-100p0" },
+	{ EQ7HC_SOUTH_DIV_XSPI_SYS,       "xspi_sys",         1, 8,   EQ7HC_SOUTH_PLL_XSPI },
+	{ EQ7HC_SOUTH_DIV_XSPI_MBITS,     "xspi_mbits",       1, 8,   EQ7HC_SOUTH_PLL_XSPI },
+	{ EQ7HC_SOUTH_DIV_NOC_S,          "noc_s",            1, 2,   EQ7HC_SOUTH_PLL_PER },
+	{ EQ7HC_SOUTH_DIV_PCIE_SYS,       "pcie_sys",         1, 4,   EQ7HC_SOUTH_PLL_PER },
+	{ EQ7HC_SOUTH_DIV_PCIE_SYS_MBITS, "pcie_sys_mbits",   1, 4,   EQ7HC_SOUTH_PLL_PER },
+	{ EQ7HC_SOUTH_DIV_PCIE_GBE_PHY,   "pcie_gbe_phy_apb", 1, 16,  EQ7HC_SOUTH_PLL_PER },
+	{ EQ7HC_SOUTH_DIV_UFS_CORE,       "ufs_core",         1, 8,   EQ7HC_SOUTH_PLL_PER },
+	{ EQ7HC_SOUTH_DIV_UFS_SMS,        "ufs_sms",          1, 5,   EQ7HC_SOUTH_PLL_PER },
+	{ EQ7HC_SOUTH_DIV_UFS_ROM_SMS,    "ufs_rom_sms",      1, 5,   EQ7HC_SOUTH_PLL_PER },
+	{ EQ7HC_SOUTH_DIV_ETH_SYS,        "eth_sys",          1, 8,   EQ7HC_SOUTH_PLL_PER },
+	{ EQ7HC_SOUTH_DIV_ETH_MBITS,      "eth_mbits",        1, 8,   EQ7HC_SOUTH_PLL_PER },
+	{ EQ7HC_SOUTH_DIV_CFG_S,          "cfg_s",            1, 8,   EQ7HC_SOUTH_PLL_PER },
+	{ EQ7HC_SOUTH_DIV_TSU,            "tsu",              1, 64,  EQ7HC_SOUTH_PLL_PER },
+	{ EQ7HC_SOUTH_DIV_VDIO,           "vdio",             1, 4,   EQ7HC_SOUTH_PLL_VDIO },
+	{ EQ7HC_SOUTH_DIV_VDIO_CORE,      "vdio_core",        1, 4,   EQ7HC_SOUTH_PLL_VDIO },
+	{ EQ7HC_SOUTH_DIV_VDIO_CORE_MBIT, "vdio_core_mbit",   1, 4,   EQ7HC_SOUTH_PLL_VDIO },
+	{ EQ7HC_SOUTH_DIV_VDO_CORE_MBITS, "vdo_core_mbits",   1, 4,   EQ7HC_SOUTH_PLL_VDIO },
+	{ EQ7HC_SOUTH_DIV_VDO_P,          "vdo_p",            1, 40,  EQ7HC_SOUTH_PLL_VDIO },
+	{ EQ7HC_SOUTH_DIV_VDIO_CFG,       "vdio_cfg",         1, 150, EQ7HC_SOUTH_PLL_VDIO },
+	{ EQ7HC_SOUTH_DIV_VDIO_TXCLKESC,  "vdio_txclkesc",    1, 8,   EQ7HC_SOUTH_PLL_VDIO },
+};
+
+static const struct eqc_early_match_data eqc_eyeq7h_south_early_match_data __initconst = {
+	.early_pll_count	= ARRAY_SIZE(eqc_eyeq7h_south_early_plls),
+	.early_plls		= eqc_eyeq7h_south_early_plls,
+
+	.early_fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_south_early_fixed_factors),
+	.early_fixed_factors		= eqc_eyeq7h_south_early_fixed_factors,
+
+	.late_clk_count		= ARRAY_SIZE(eqc_eyeq7h_south_plls) +
+				  ARRAY_SIZE(eqc_eyeq7h_south_fixed_factors),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_south_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_south_plls),
+	.plls		= eqc_eyeq7h_south_plls,
+
+	.fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_south_fixed_factors),
+	.fixed_factors		= eqc_eyeq7h_south_fixed_factors,
+
+	.reset_auxdev_name = "reset_south",
+
+	.early_clk_count = ARRAY_SIZE(eqc_eyeq7h_south_early_plls) +
+			   ARRAY_SIZE(eqc_eyeq7h_south_early_fixed_factors),
+};
+
+/* Required early as reference for other PLL in OLB east */
+static const struct eqc_pll eqc_eyeq7h_east_early_plls[] = {
+	{ EQ7HC_EAST_PLL_106P6, "pll-106p6-e", 0x0, EQC_PLL_JFRACR },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_east_early_fixed_factors[] = {
+	{ EQ7HC_EAST_DIV_REF_106P6, "ref_106p6_e", 1, 40, EQ7HC_EAST_PLL_106P6 },
+};
+
+static const struct eqc_pll eqc_eyeq7h_east_plls[] = {
+	//{index, name, reg, type, parent}
+	{ EQ7HC_EAST_PLL_NOC, "pll-noc-e", 0x30, EQC_PLL_AINTP, "ref_106p6_e" },
+	{ EQ7HC_EAST_PLL_ISP, "pll-isp",   0x38, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_EAST_PLL_VEU, "pll-veu",   0x40, EQC_PLL_AINTP, "ref_100p0" },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_east_fixed_factors[] = {
+	{ EQ7HC_EAST_DIV_REF_DDR_PHY, "ref_ddr_phy_e", 1, 2,  EQ7HC_EAST_PLL_106P6, "pll-106p6-e" },
+	{ EQ7HC_EAST_DIV_CORE,        "core_e",        1, 2,  EQ7HC_EAST_PLL_NOC },
+	{ EQ7HC_EAST_DIV_CORE_MBITS,  "core_mbits_e",  1, 2,  EQ7HC_EAST_PLL_NOC },
+	{ EQ7HC_EAST_DIV_ISRAM_MBITS, "isram_mbits_e", 1, 2,  EQ7HC_EAST_PLL_NOC },
+	{ EQ7HC_EAST_DIV_CFG,         "cfg_e",         1, 4,  EQ7HC_EAST_PLL_NOC },
+	{ EQ7HC_EAST_DIV_VEU_CORE,    "veu_core",      1, 4,  EQ7HC_EAST_PLL_VEU },
+	{ EQ7HC_EAST_DIV_VEU_MBITS,   "veu_mbits",     1, 4,  EQ7HC_EAST_PLL_VEU },
+	{ EQ7HC_EAST_DIV_VEU_OCP,     "veu_ocp",       1, 16, EQ7HC_EAST_PLL_VEU },
+	{ EQ7HC_EAST_DIV_LBITS,       "lbits_e",       1, 48, EQ7HC_EAST_PLL_ISP },
+	{ EQ7HC_EAST_DIV_ISP0_CORE,   "isp0_core",     1, 2,  EQ7HC_EAST_PLL_ISP },
+};
+
+static const struct eqc_early_match_data eqc_eyeq7h_east_early_match_data __initconst = {
+	.early_pll_count	= ARRAY_SIZE(eqc_eyeq7h_east_early_plls),
+	.early_plls		= eqc_eyeq7h_east_early_plls,
+
+	.early_fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_east_early_fixed_factors),
+	.early_fixed_factors		= eqc_eyeq7h_east_early_fixed_factors,
+
+	.late_clk_count		= ARRAY_SIZE(eqc_eyeq7h_east_plls) +
+	ARRAY_SIZE(eqc_eyeq7h_east_fixed_factors),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_east_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_east_plls),
+	.plls		= eqc_eyeq7h_east_plls,
+
+	.fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_east_fixed_factors),
+	.fixed_factors		= eqc_eyeq7h_east_fixed_factors,
+
+	.reset_auxdev_name = "reset_east",
+
+	.early_clk_count = ARRAY_SIZE(eqc_eyeq7h_east_early_plls) +
+	ARRAY_SIZE(eqc_eyeq7h_east_early_fixed_factors),
+};
+
+/* Required early as reference for other PLL in OLB west */
+static const struct eqc_pll eqc_eyeq7h_west_early_plls[] = {
+	{ EQ7HC_WEST_PLL_106P6, "pll-106p6-w", 0x0, EQC_PLL_JFRACR },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_west_early_fixed_factors[] = {
+	{ EQ7HC_WEST_DIV_REF_106P6, "ref_106p6_w", 1, 40, EQ7HC_WEST_PLL_106P6 },
+};
+
+static const struct eqc_pll eqc_eyeq7h_west_plls[] = {
+	//{index, name, reg, type, parent}
+	{ EQ7HC_WEST_PLL_NOC, "pll-noc-w", 0x30, EQC_PLL_AINTP, "ref_106p6_w" },
+	{ EQ7HC_WEST_PLL_GPU, "pll-gpu",   0x38, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_WEST_PLL_SSI, "pll-ssi",   0x40, EQC_PLL_AINTP, "ref_100p0" },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_west_fixed_factors[] = {
+	{ EQ7HC_WEST_DIV_GPU,            "gpu",            1, 2,  EQ7HC_WEST_PLL_GPU },
+	{ EQ7HC_WEST_DIV_GPU_MBITS,      "gpu_mbits",      1, 2,  EQ7HC_WEST_PLL_GPU },
+	{ EQ7HC_WEST_DIV_LBITS,          "lbits_w",        1, 40, EQ7HC_WEST_PLL_GPU },
+	{ EQ7HC_WEST_DIV_MIPS_TIMER,     "mips_timer",     1, 24, EQ7HC_WEST_PLL_SSI },
+	{ EQ7HC_WEST_DIV_SSI_CORE,       "ssi_core",       1, 2,  EQ7HC_WEST_PLL_SSI },
+	{ EQ7HC_WEST_DIV_SSI_CORE_MBITS, "ssi_core_mbits", 1, 2,  EQ7HC_WEST_PLL_SSI },
+	{ EQ7HC_WEST_DIV_SSI_ROM,        "ssi_rom",        1, 8,  EQ7HC_WEST_PLL_SSI },
+	{ EQ7HC_WEST_DIV_SSI_ROM_MBITS,  "ssi_rom_mbits",  1, 8,  EQ7HC_WEST_PLL_SSI },
+	{ EQ7HC_WEST_DIV_REF_DDR_PHY,    "ref_ddr_phy_w",  1, 2,  EQ7HC_WEST_PLL_106P6,
+	  "pll-106p6-w" },
+	{ EQ7HC_WEST_DIV_CORE,           "core_w",         1, 2,  EQ7HC_WEST_PLL_NOC },
+	{ EQ7HC_WEST_DIV_CORE_MBIT,      "core_mbit_w",    1, 2,  EQ7HC_WEST_PLL_NOC },
+	{ EQ7HC_WEST_DIV_CFG,            "cfg_w",          1, 4,  EQ7HC_WEST_PLL_NOC },
+	{ EQ7HC_WEST_DIV_CAU,            "cau_w",          1, 8,  EQ7HC_WEST_PLL_NOC },
+	{ EQ7HC_WEST_DIV_CAU_MBITS,      "cau_mbits_w",    1, 8,  EQ7HC_WEST_PLL_NOC },
+};
+
+static const struct eqc_early_match_data eqc_eyeq7h_west_early_match_data __initconst = {
+	.early_pll_count	= ARRAY_SIZE(eqc_eyeq7h_west_early_plls),
+	.early_plls		= eqc_eyeq7h_west_early_plls,
+
+	.early_fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_west_early_fixed_factors),
+	.early_fixed_factors		= eqc_eyeq7h_west_early_fixed_factors,
+
+	.late_clk_count		= ARRAY_SIZE(eqc_eyeq7h_west_plls) +
+				  ARRAY_SIZE(eqc_eyeq7h_west_fixed_factors),
+};
+
+static const struct eqc_match_data eqc_eyeq7h_west_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_west_plls),
+	.plls		= eqc_eyeq7h_west_plls,
+
+	.fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_west_fixed_factors),
+	.fixed_factors		= eqc_eyeq7h_west_fixed_factors,
+
+	.reset_auxdev_name = "reset_west",
+
+	.early_clk_count = ARRAY_SIZE(eqc_eyeq7h_west_early_plls) +
+			   ARRAY_SIZE(eqc_eyeq7h_west_early_fixed_factors),
+};
+
+static const struct eqc_pll eqc_eyeq7h_periph_east_plls[] = {
+	//{index, name, reg, type, parent}
+	{ EQ7HC_PERIPH_EAST_PLL_PER, "pll-periph_east_per", 0x0, EQC_PLL_AINTP },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_periph_east_fixed_factors[] = {
+	{ EQ7HC_PERIPH_EAST_DIV_PER, "periph_e", 1, 10, EQ7HC_PERIPH_EAST_PLL_PER },
+};
+
+static const struct eqc_match_data eqc_eyeq7h_periph_east_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_periph_east_plls),
+	.plls		= eqc_eyeq7h_periph_east_plls,
+
+	.fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_periph_east_fixed_factors),
+	.fixed_factors		= eqc_eyeq7h_periph_east_fixed_factors,
+
+	.reset_auxdev_name = "reset_periph_east",
+};
+
+static const struct eqc_pll eqc_eyeq7h_periph_west_plls[] = {
+	//{index, name, reg, type, parent}
+	{ EQ7HC_PERIPH_WEST_PLL_PER, "pll-periph_west_per", 0x0, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_PERIPH_WEST_PLL_I2S, "pll-periph_west_i2s", 0x4, EQC_PLL_AINTP, "ref_106p6_w" },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_periph_west_fixed_factors[] = {
+	{ EQ7HC_PERIPH_WEST_DIV_PER, "periph_w",         1, 10, EQ7HC_PERIPH_WEST_PLL_PER },
+	{ EQ7HC_PERIPH_WEST_DIV_I2S, "periph_i2s_ser_w", 1, 100, EQ7HC_PERIPH_WEST_PLL_I2S },
+};
+
+static const struct eqc_match_data eqc_eyeq7h_periph_west_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_periph_west_plls),
+	.plls		= eqc_eyeq7h_periph_west_plls,
+
+	.fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_periph_west_fixed_factors),
+	.fixed_factors		= eqc_eyeq7h_periph_west_fixed_factors,
+
+	.reset_auxdev_name = "reset_periph_west",
+};
+
+static const struct clk_div_table eqc_eyeq7h_ddr_apb_div_table[] = {
+	{ .val = 0, .div = 8 },
+	{ .val = 1, .div = 128 },
+	{ .val = 0, .div = 0 },
+};
+
+static const struct clk_div_table eqc_eyeq7h_ddr_ref_div_table[] = {
+	{ .val = 0, .div = 2 },
+	{ .val = 1, .div = 8 },
+	{ .val = 0, .div = 0 },
+};
+
+static const struct clk_div_table eqc_eyeq7h_ddr_dfi_div_table[] = {
+	{ .val = 0, .div = 2 },
+	{ .val = 1, .div = 32 },
+	{ .val = 0, .div = 0 },
+};
+
+static const struct eqc_div eqc_eyeq7h_ddr0_divs[] = {
+	{
+		.index = EQ7HC_DDR_DIV_APB,
+		.name = "div-ddr0_apb",
+		.parent_idx = EQ7HC_DDR_PLL,
+		.reg = 0x08,
+		.shift = 10,
+		.width = 1,
+		.table = eqc_eyeq7h_ddr_apb_div_table,
+	},
+	{
+		.index = EQ7HC_DDR_DIV_PLLREF,
+		.name = "div-ddr0_pllref",
+		.parent_idx = EQ7HC_DDR_PLL,
+		.reg = 0x08,
+		.shift = 10,
+		.width = 1,
+		.table = eqc_eyeq7h_ddr_ref_div_table,
+	},
+	{
+		.index = EQ7HC_DDR_DIV_DFI,
+		.name = "div-ddr0-dfi",
+		.parent_idx = EQ7HC_DDR_PLL,
+		.reg = 0x08,
+		.shift = 10,
+		.width = 1,
+		.table = eqc_eyeq7h_ddr_dfi_div_table,
+	},
+};
+
+static const struct eqc_pll eqc_eyeq7h_ddr0_plls[] = {
+	//{index, name, reg, type, parent}
+	{ EQ7HC_DDR_PLL, "pll-ddr0", 0x0, EQC_PLL_AINTP },
+};
+
+static const struct eqc_match_data eqc_eyeq7h_ddr0_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_ddr0_plls),
+	.plls		= eqc_eyeq7h_ddr0_plls,
+
+	.div_count	= ARRAY_SIZE(eqc_eyeq7h_ddr0_divs),
+	.divs		= eqc_eyeq7h_ddr0_divs,
+
+	.reset_auxdev_name = "reset_ddr0",
+};
+
+static const struct eqc_div eqc_eyeq7h_ddr1_divs[] = {
+	{
+		.index = EQ7HC_DDR_DIV_APB,
+		.name = "div-ddr1_apb",
+		.parent_idx = EQ7HC_DDR_PLL,
+		.reg = 0x08,
+		.shift = 10,
+		.width = 1,
+		.table = eqc_eyeq7h_ddr_apb_div_table,
+	},
+	{
+		.index = EQ7HC_DDR_DIV_PLLREF,
+		.name = "div-ddr1_pllref",
+		.parent_idx = EQ7HC_DDR_PLL,
+		.reg = 0x08,
+		.shift = 10,
+		.width = 1,
+		.table = eqc_eyeq7h_ddr_ref_div_table,
+	},
+	{
+		.index = EQ7HC_DDR_DIV_DFI,
+		.name = "div-ddr1-dfi",
+		.parent_idx = EQ7HC_DDR_PLL,
+		.reg = 0x08,
+		.shift = 10,
+		.width = 1,
+		.table = eqc_eyeq7h_ddr_dfi_div_table,
+	},
+};
+
+static const struct eqc_pll eqc_eyeq7h_ddr1_plls[] = {
+	//{index, name, reg, type, parent}
+	{ EQ7HC_DDR_PLL, "pll-ddr1", 0x0, EQC_PLL_AINTP },
+};
+
+static const struct eqc_match_data eqc_eyeq7h_ddr1_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_ddr1_plls),
+	.plls		= eqc_eyeq7h_ddr1_plls,
+
+	.div_count	= ARRAY_SIZE(eqc_eyeq7h_ddr1_divs),
+	.divs		= eqc_eyeq7h_ddr1_divs,
+
+	.reset_auxdev_name = "reset_ddr1",
+};
+
+static const struct eqc_pll eqc_eyeq7h_mips0_plls[] = {
+	{ EQ7HC_MIPS_PLL_CPU, "pll-cpu0", 0x0, EQC_PLL_AINTP },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_mips0_fixed_factors[] = {
+	{ EQ7HC_MIPS_DIV_CM, "mips0_cm", 1, 2, EQ7HC_MIPS_PLL_CPU },
+};
+
+static const struct eqc_match_data eqc_eyeq7h_mips0_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_mips0_plls),
+	.plls		= eqc_eyeq7h_mips0_plls,
+
+	.fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_mips0_fixed_factors),
+	.fixed_factors		= eqc_eyeq7h_mips0_fixed_factors,
+};
+
+static const struct eqc_pll eqc_eyeq7h_mips1_plls[] = {
+	{ EQ7HC_MIPS_PLL_CPU, "pll-cpu1", 0x0, EQC_PLL_AINTP },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_mips1_fixed_factors[] = {
+	{ EQ7HC_MIPS_DIV_CM, "mips1_cm", 1, 2, EQ7HC_MIPS_PLL_CPU },
+};
+
+static const struct eqc_match_data eqc_eyeq7h_mips1_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_mips1_plls),
+	.plls		= eqc_eyeq7h_mips1_plls,
+
+	.fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_mips1_fixed_factors),
+	.fixed_factors		= eqc_eyeq7h_mips1_fixed_factors,
+};
+
+static const struct eqc_pll eqc_eyeq7h_mips2_plls[] = {
+	{ EQ7HC_MIPS_PLL_CPU, "pll-cpu2", 0x0, EQC_PLL_AINTP },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_mips2_fixed_factors[] = {
+	{ EQ7HC_MIPS_DIV_CM, "mips2_cm", 1, 2, EQ7HC_MIPS_PLL_CPU },
+};
+
+static const struct eqc_match_data eqc_eyeq7h_mips2_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_mips2_plls),
+	.plls		= eqc_eyeq7h_mips2_plls,
+
+	.fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_mips2_fixed_factors),
+	.fixed_factors		= eqc_eyeq7h_mips2_fixed_factors,
+};
+
+static const struct eqc_pll eqc_eyeq7h_acc0_plls[] = {
+	//{index, name, reg, type, parent}
+	{ EQ7HC_ACC_PLL_VMP, "pll-acc0-vmp",     0x400, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_ACC_PLL_MPC, "pll-acc0-mpc",     0x404, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_ACC_PLL_PMA, "pll-acc0-pma",     0x408, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_ACC_PLL_NOC, "pll-acc0-noc-acc", 0x40c, EQC_PLL_AINTP, "ref_106p6_e" },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_acc0_fixed_factors[] = {
+	{ EQ7HC_ACC_DIV_PMA,   "acc0_pma",   1, 2, EQ7HC_ACC_PLL_PMA },
+	{ EQ7HC_ACC_DIV_NCORE, "acc0_ncore", 1, 2, EQ7HC_ACC_PLL_NOC },
+	{ EQ7HC_ACC_DIV_CFG,   "acc0_cfg",   1, 8, EQ7HC_ACC_PLL_NOC },
+};
+
+static const struct eqc_match_data eqc_eyeq7h_acc0_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_acc0_plls),
+	.plls		= eqc_eyeq7h_acc0_plls,
+
+	.fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_acc0_fixed_factors),
+	.fixed_factors		= eqc_eyeq7h_acc0_fixed_factors,
+
+	.reset_auxdev_name = "reset_acc0",
+};
+
+static const struct eqc_pll eqc_eyeq7h_acc1_plls[] = {
+	//{index, name, reg, type, parent}
+	{ EQ7HC_ACC_PLL_VMP, "pll-acc1-vmp",     0x400, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_ACC_PLL_MPC, "pll-acc1-mpc",     0x404, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_ACC_PLL_PMA, "pll-acc1-pma",     0x408, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_ACC_PLL_NOC, "pll-acc1-noc-acc", 0x40c, EQC_PLL_AINTP, "ref_106p6_e" },
+};
+
+static const struct eqc_match_data eqc_eyeq7h_acc1_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_acc1_plls),
+	.plls		= eqc_eyeq7h_acc1_plls,
+
+	.reset_auxdev_name = "reset_acc1",
+};
+
+static const struct eqc_pll eqc_eyeq7h_xnn0_plls[] = {
+	//{index, name, reg, type, parent}
+	{ EQ7HC_XNN_PLL_XNN0,  "pll-xnn0-0",     0x400, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_XNN_PLL_XNN1,  "pll-xnn0-1",     0x404, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_XNN_PLL_XNN2,  "pll-xnn0-2",     0x408, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_XNN_PLL_CLSTR, "pll-xnn0-clstr", 0x410, EQC_PLL_AINTP, "ref_106p6_e" },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq7h_xnn0_fixed_factors[] = {
+	{ EQ7HC_XNN_DIV_XNN0,   "xnn0",        1, 2, EQ7HC_XNN_PLL_XNN0 },
+	{ EQ7HC_XNN_DIV_XNN1,   "xnn1",        1, 2, EQ7HC_XNN_PLL_XNN1 },
+	{ EQ7HC_XNN_DIV_XNN2,   "xnn2",        1, 2, EQ7HC_XNN_PLL_XNN2 },
+	{ EQ7HC_XNN_DIV_CLSTR,  "xnn0_clstr",  1, 2, EQ7HC_XNN_PLL_CLSTR },
+	{ EQ7HC_XNN_DIV_I2,     "xnn0_i2",     1, 4, EQ7HC_XNN_PLL_CLSTR },
+	{ EQ7HC_XNN_DIV_I2_SMS, "xnn0_i2_sms", 1, 4, EQ7HC_XNN_PLL_CLSTR },
+	{ EQ7HC_XNN_DIV_CFG,    "xnn0_cfg",    1, 8, EQ7HC_XNN_PLL_CLSTR },
+};
+
+static const struct eqc_match_data eqc_eyeq7h_xnn0_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_xnn0_plls),
+	.plls		= eqc_eyeq7h_xnn0_plls,
+
+	.fixed_factor_count	= ARRAY_SIZE(eqc_eyeq7h_xnn0_fixed_factors),
+	.fixed_factors		= eqc_eyeq7h_xnn0_fixed_factors,
+
+	.reset_auxdev_name = "reset_xnn0",
+};
+
+static const struct eqc_pll eqc_eyeq7h_xnn1_plls[] = {
+	//{index, name, reg, type, parent}
+	{ EQ7HC_XNN_PLL_XNN0,  "pll-xnn1-0",     0x400, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_XNN_PLL_XNN1,  "pll-xnn1-1",     0x404, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_XNN_PLL_XNN2,  "pll-xnn1-2",     0x408, EQC_PLL_AINTP, "ref_100p0" },
+	{ EQ7HC_XNN_PLL_CLSTR, "pll-xnn1-clstr", 0x410, EQC_PLL_AINTP, "ref_106p6_e" },
+};
+
+static const struct eqc_match_data eqc_eyeq7h_xnn1_match_data = {
+	.pll_count	= ARRAY_SIZE(eqc_eyeq7h_xnn1_plls),
+	.plls		= eqc_eyeq7h_xnn1_plls,
+
+	.reset_auxdev_name = "reset_xnn1",
+};
+
 static const struct of_device_id eqc_match_table[] = {
 	{ .compatible = "mobileye,eyeq5-olb", .data = &eqc_eyeq5_match_data },
 	{ .compatible = "mobileye,eyeq6l-olb", .data = &eqc_eyeq6l_match_data },
@@ -833,6 +1291,22 @@ static const struct of_device_id eqc_match_table[] = {
 	{ .compatible = "mobileye,eyeq6h-ddr0-olb", .data = &eqc_eyeq6h_ddr0_match_data },
 	{ .compatible = "mobileye,eyeq6h-ddr1-olb", .data = &eqc_eyeq6h_ddr1_match_data },
 	{ .compatible = "mobileye,eyeq6h-acc-olb", .data = &eqc_eyeq6h_acc_match_data },
+	{ .compatible = "mobileye,eyeq7h-periph-west-olb",
+	  .data = &eqc_eyeq7h_periph_west_match_data },
+	{ .compatible = "mobileye,eyeq7h-periph-east-olb",
+	  .data = &eqc_eyeq7h_periph_east_match_data },
+	{ .compatible = "mobileye,eyeq7h-west-olb", .data = &eqc_eyeq7h_west_match_data },
+	{ .compatible = "mobileye,eyeq7h-east-olb", .data = &eqc_eyeq7h_east_match_data },
+	{ .compatible = "mobileye,eyeq7h-south-olb", .data = &eqc_eyeq7h_south_match_data },
+	{ .compatible = "mobileye,eyeq7h-mips0-olb", .data = &eqc_eyeq7h_mips0_match_data },
+	{ .compatible = "mobileye,eyeq7h-mips1-olb", .data = &eqc_eyeq7h_mips1_match_data },
+	{ .compatible = "mobileye,eyeq7h-mips2-olb", .data = &eqc_eyeq7h_mips2_match_data },
+	{ .compatible = "mobileye,eyeq7h-ddr0-olb", .data = &eqc_eyeq7h_ddr0_match_data },
+	{ .compatible = "mobileye,eyeq7h-ddr1-olb", .data = &eqc_eyeq7h_ddr1_match_data },
+	{ .compatible = "mobileye,eyeq7h-acc0-olb", .data = &eqc_eyeq7h_acc0_match_data },
+	{ .compatible = "mobileye,eyeq7h-acc1-olb", .data = &eqc_eyeq7h_acc1_match_data },
+	{ .compatible = "mobileye,eyeq7h-xnn0-olb", .data = &eqc_eyeq7h_xnn0_match_data },
+	{ .compatible = "mobileye,eyeq7h-xnn1-olb", .data = &eqc_eyeq7h_xnn1_match_data },
 	{}
 };
 
@@ -1004,3 +1478,24 @@ static void __init eqc_eyeq6h_west_early_init(struct device_node *np)
 }
 CLK_OF_DECLARE_DRIVER(eqc_eyeq6h_west, "mobileye,eyeq6h-west-olb",
 		      eqc_eyeq6h_west_early_init);
+
+static void __init eqc_eyeq7h_south_early_init(struct device_node *np)
+{
+	eqc_early_init(np, &eqc_eyeq7h_south_early_match_data);
+}
+CLK_OF_DECLARE_DRIVER(eqc_eyeq7h_south, "mobileye,eyeq7h-south-olb",
+		      eqc_eyeq7h_south_early_init);
+
+static void __init eqc_eyeq7h_east_early_init(struct device_node *np)
+{
+	eqc_early_init(np, &eqc_eyeq7h_east_early_match_data);
+}
+CLK_OF_DECLARE_DRIVER(eqc_eyeq7h_east, "mobileye,eyeq7h-east-olb",
+		      eqc_eyeq7h_east_early_init);
+
+static void __init eqc_eyeq7h_west_early_init(struct device_node *np)
+{
+	eqc_early_init(np, &eqc_eyeq7h_west_early_match_data);
+}
+CLK_OF_DECLARE_DRIVER(eqc_eyeq7h_west, "mobileye,eyeq7h-west-olb",
+		      eqc_eyeq7h_west_early_init);

-- 
2.51.0

Re: [PATCH 01/19] dt-bindings: soc: mobileye: rename to eyeq-olb.yaml

[Krzysztof Kozlowski]

On Wed, Sep 03, 2025 at 02:47:08PM +0200, Benoît Monin wrote:
> Drop the 5 from the binding name as the OLB described in it are found
> in multiple Mobileye eyeQ SoCs.
> 
> The binding already contains entries for eyeQ6L and eyeQ6H OLBs
> alongside the one for the eyeQ5.
> 
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  .../soc/mobileye/{mobileye,eyeq5-olb.yaml => mobileye,eyeq-olb.yaml}    | 2 +-

No, we don't do that. That's unneeded churn.

If you wanted to rename, you could try when adding new compatibles. And
maybe you even tried and received comment for that.

NAK

Best regards,
Krzysztof

Re: [PATCH 03/19] dt-bindings: soc: mobileye: add eyeQ7H compatibles

[Krzysztof Kozlowski]

On Wed, Sep 03, 2025 at 02:47:10PM +0200, Benoît Monin wrote:
>  patternProperties:
>    '-pins?$':
> @@ -265,6 +279,88 @@ required:
>  additionalProperties: false
>  
>  allOf:
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - mobileye,eyeq5-olb
> +              - mobileye,eyeq6l-olb
> +              - mobileye,eyeq6h-acc-olb
> +              - mobileye,eyeq6h-central-olb
> +              - mobileye,eyeq6h-east-olb
> +              - mobileye,eyeq6h-west-olb
> +              - mobileye,eyeq6h-south-olb
> +              - mobileye,eyeq6h-ddr0-olb
> +              - mobileye,eyeq6h-ddr1-olb
> +              - mobileye,eyeq7h-south-olb
> +              - mobileye,eyeq7h-periph-east-olb
> +              - mobileye,eyeq7h-ddr0-olb
> +              - mobileye,eyeq7h-ddr1-olb
> +              - mobileye,eyeq7h-mips0-olb
> +              - mobileye,eyeq7h-mips1-olb
> +              - mobileye,eyeq7h-mips2-olb
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 1

Drop

> +          maxItems: 1
> +        clock-names:
> +          items:
> +            - const: ref
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - mobileye,eyeq7h-east-olb
> +              - mobileye,eyeq7h-west-olb
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 2
> +          maxItems: 2
> +        clock-names:
> +          items:
> +            - const: ref
> +            - const: ref_100p0
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - mobileye,eyeq7h-periph-west-olb
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 2
> +          maxItems: 2
> +        clock-names:
> +          items:
> +            - const: ref_100p0
> +            - const: ref_106p6_w
> +
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - mobileye,eyeq7h-acc0-olb
> +              - mobileye,eyeq7h-acc1-olb
> +              - mobileye,eyeq7h-xnn0-olb
> +              - mobileye,eyeq7h-xnn1-olb
> +    then:
> +      properties:
> +        clocks:
> +          minItems: 2
> +          maxItems: 2
> +        clock-names:
> +          items:
> +            - const: ref_100p0
> +            - const: ref_106p6_e

That's the same as previous ref_106p6_w.

These are not names of clocks. These are names of inputs.


> +
>      # Compatibles exposing a single reset domain.
>    - if:
>        properties:
> @@ -274,6 +370,12 @@ allOf:
>                - mobileye,eyeq6h-acc-olb
>                - mobileye,eyeq6h-east-olb
>                - mobileye,eyeq6h-west-olb
> +              - mobileye,eyeq7h-east-olb
> +              - mobileye,eyeq7h-west-olb
> +              - mobileye,eyeq7h-periph-east-olb
> +              - mobileye,eyeq7h-periph-west-olb
> +              - mobileye,eyeq7h-ddr0-olb
> +              - mobileye,eyeq7h-ddr1-olb
>      then:
>        properties:
>          '#reset-cells':
> @@ -289,6 +391,11 @@ allOf:
>              enum:
>                - mobileye,eyeq5-olb
>                - mobileye,eyeq6l-olb
> +              - mobileye,eyeq7h-south-olb
> +              - mobileye,eyeq7h-acc0-olb
> +              - mobileye,eyeq7h-acc1-olb
> +              - mobileye,eyeq7h-xnn0-olb
> +              - mobileye,eyeq7h-xnn1-olb
>      then:
>        properties:
>          '#reset-cells':
> @@ -306,6 +413,9 @@ allOf:
>                - mobileye,eyeq6h-south-olb
>                - mobileye,eyeq6h-ddr0-olb
>                - mobileye,eyeq6h-ddr1-olb
> +              - mobileye,eyeq7h-mips0-olb
> +              - mobileye,eyeq7h-mips1-olb
> +              - mobileye,eyeq7h-mips2-olb
>      then:
>        properties:
>          '#reset-cells': false
> @@ -350,3 +460,18 @@ examples:
>          clock-names = "ref";
>        };
>      };
> +  - |
> +    soc {
> +      #address-cells = <2>;
> +      #size-cells = <2>;
> +
> +      system-controller0@45000000 {
> +        compatible = "mobileye,eyeq7h-acc0-olb", "syscon";

No need for new example for difference in one property.

Best regards,
Krzysztof

Re: [PATCH 04/19] dt-bindings: clock: mobileye: add eyeQ7H clock indexes

[Krzysztof Kozlowski]

On Wed, Sep 03, 2025 at 02:47:11PM +0200, Benoît Monin wrote:
> Add the clock indexes for the various OLB found in the eyeQ7H SoC.
> For some of the OLB, the indexes are common between two or three
> blocks:
> * EQ7HC_DDR defines the clock indexes of DDR0 and DDR1 OLB.
> * EQ7HC_MIPS defines the clock indexes of MIPS0, MIPS1, and MIPS2 OLB.
> * EQ7HC_ACC defines the clock indexes of ACC0 and ACC1 OLB.
> * EQ7HC_XNN defines the clock indexes of XNN0 and XNN1 OLB.
> 
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  include/dt-bindings/clock/mobileye,eyeq-clk.h | 110 ++++++++++++++++++++++++++
>  1 file changed, 110 insertions(+)
> 
> diff --git a/include/dt-bindings/clock/mobileye,eyeq-clk.h b/include/dt-bindings/clock/mobileye,eyeq-clk.h
> index 8424ec59a02d037ddd5b049cb4b7f26764ae2542..0fe9b98c940cbc479ce46fc83fc651101bf1b86a 100644
> --- a/include/dt-bindings/clock/mobileye,eyeq-clk.h
> +++ b/include/dt-bindings/clock/mobileye,eyeq-clk.h

This is not a separate patch.

Best regards,
Krzysztof

Re: [PATCH 02/19] dt-bindings: clock: mobileye: rename to eyeq-clk.h

[Krzysztof Kozlowski]

On Wed, Sep 03, 2025 at 02:47:09PM +0200, Benoît Monin wrote:
> Rename the header from mobileye,eyeq5-clk.h to mobileye,eyeq-clk.h as
> it covers more SoCs than just the eyeQ5, but also the eyeQ6L and
> eyeQ6H.
> 
> Also changes all includes to point to the renamed header.
> 
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  MAINTAINERS                                                           | 2 +-
>  arch/mips/boot/dts/mobileye/eyeq5.dtsi                                | 2 +-
>  arch/mips/boot/dts/mobileye/eyeq6h.dtsi                               | 2 +-
>  drivers/clk/clk-eyeq.c                                                | 2 +-
>  .../dt-bindings/clock/{mobileye,eyeq5-clk.h => mobileye,eyeq-clk.h}   | 4 ++--

NAK, stop doing such renames.

Look how other well upstreamed SoCs are doing this - you want file per
SoC variant, so you want SEPARATE eyeq7 header.

Best regards,
Krzysztof

Re: [PATCH 05/19] dt-bindings: reset: add Mobileye eyeQ

[Krzysztof Kozlowski]

On Wed, Sep 03, 2025 at 02:47:12PM +0200, Benoît Monin wrote:
> Define the indexes of the reset controllers present in 11 of the OLB
> found in Mobileye eyeQ7H SoC. The define names start with EQ7HR, which
> is the abbreviation of EyeQ7H Reset.
> 
> For the OLBs with multiple reset domains, the domain number is in the
> define name (DOMx) and should also be passed in the device tree:
> 
>     resets = <&olb_south 0 EQ7HR_SOUTH_DOM0_PCI_CTL>;
> 
> For the OLBs with a single reset domain, only the reset index is needed:
> 
>     resets = <&olb_periph_west EQ7HR_PERIPH_UART>;
> 
> Some reset indexes are common between two OLB:
> * EQ7HR_PERIPH defines the reset indexes of OLB periph_east and
>   periph_west.
> * EQ7HR_DDR defines the reset indexes of OLB ddr0 and ddr1.
> * EQ7HR_ACC defines the reset indexes of OLB acc0 and acc1.
> * EQ7HR_XNN defines the reset indexes of OLB xnn0 and xnn1.
> 
> Signed-off-by: Sari Khoury <sari.khoury@mobileye.com>
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  MAINTAINERS                                     |  1 +
>  include/dt-bindings/reset/mobileye,eyeq-reset.h | 75 +++++++++++++++++++++++++

That's not a separate patch. Binding headers go with bindings.

Best regards,
Krzysztof