* [PATCH 1/7] dt-bindings: soc: mobileye: OLB is an Ethernet PHY provider on EyeQ5
2025-10-22 15:39 [PATCH 0/7] Add generic PHY driver used by MACB/GEM on EyeQ5 Théo Lebrun
@ 2025-10-22 15:39 ` Théo Lebrun
2025-10-22 17:55 ` Conor Dooley
2025-10-22 15:39 ` [PATCH 2/7] phy: Add driver for EyeQ5 Ethernet PHY wrapper Théo Lebrun
` (5 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Théo Lebrun @ 2025-10-22 15:39 UTC (permalink / raw)
To: Vladimir Kondratiev, Grégory Clement, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Michael Turquette, Stephen Boyd,
Philipp Zabel, Thomas Bogendoerfer
Cc: linux-mips, devicetree, linux-kernel, linux-phy, linux-clk,
Benoît Monin, Maxime Chevallier, Tawfik Bayouk,
Thomas Petazzoni, Théo Lebrun
OLB on EyeQ5 ("mobileye,eyeq5-olb" compatible) is now declared as a
generic PHY provider. Under the hood, it provides Ethernet RGMII/SGMII
PHY support for both MAC instances.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
.../devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
index 6d11472ba5a7..56401d76a9b5 100644
--- a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
+++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq5-olb.yaml
@@ -51,6 +51,9 @@ properties:
clock-names:
const: ref
+ '#phy-cells':
+ const: 1
+
patternProperties:
'-pins?$':
type: object
@@ -310,7 +313,7 @@ allOf:
properties:
'#reset-cells': false
- # Only EyeQ5 has pinctrl in OLB.
+ # Only EyeQ5 has pinctrl and PHY in OLB.
- if:
not:
properties:
@@ -320,6 +323,8 @@ allOf:
then:
patternProperties:
'-pins?$': false
+ properties:
+ '#phy-cells': false
examples:
- |
--
2.51.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 1/7] dt-bindings: soc: mobileye: OLB is an Ethernet PHY provider on EyeQ5
2025-10-22 15:39 ` [PATCH 1/7] dt-bindings: soc: mobileye: OLB is an Ethernet PHY provider " Théo Lebrun
@ 2025-10-22 17:55 ` Conor Dooley
0 siblings, 0 replies; 10+ messages in thread
From: Conor Dooley @ 2025-10-22 17:55 UTC (permalink / raw)
To: Théo Lebrun
Cc: Vladimir Kondratiev, Grégory Clement, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Michael Turquette, Stephen Boyd,
Philipp Zabel, Thomas Bogendoerfer, linux-mips, devicetree,
linux-kernel, linux-phy, linux-clk, Benoît Monin,
Maxime Chevallier, Tawfik Bayouk, Thomas Petazzoni
[-- Attachment #1: Type: text/plain, Size: 387 bytes --]
On Wed, Oct 22, 2025 at 05:39:03PM +0200, Théo Lebrun wrote:
> OLB on EyeQ5 ("mobileye,eyeq5-olb" compatible) is now declared as a
> generic PHY provider. Under the hood, it provides Ethernet RGMII/SGMII
> PHY support for both MAC instances.
>
> Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Acked-by: Conor Dooley <conor.dooley@microchip.com>
pw-bot: not-applicable
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 2/7] phy: Add driver for EyeQ5 Ethernet PHY wrapper
2025-10-22 15:39 [PATCH 0/7] Add generic PHY driver used by MACB/GEM on EyeQ5 Théo Lebrun
2025-10-22 15:39 ` [PATCH 1/7] dt-bindings: soc: mobileye: OLB is an Ethernet PHY provider " Théo Lebrun
@ 2025-10-22 15:39 ` Théo Lebrun
2025-10-29 15:42 ` Théo Lebrun
2025-10-22 15:39 ` [PATCH 3/7] clk: eyeq: use the auxiliary device creation helper Théo Lebrun
` (4 subsequent siblings)
6 siblings, 1 reply; 10+ messages in thread
From: Théo Lebrun @ 2025-10-22 15:39 UTC (permalink / raw)
To: Vladimir Kondratiev, Grégory Clement, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Michael Turquette, Stephen Boyd,
Philipp Zabel, Thomas Bogendoerfer
Cc: linux-mips, devicetree, linux-kernel, linux-phy, linux-clk,
Benoît Monin, Maxime Chevallier, Tawfik Bayouk,
Thomas Petazzoni, Théo Lebrun
EyeQ5 embeds a system-controller called OLB. It features many unrelated
registers, and some of those are registers used to configure the
integration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances.
Wrap in a neat generic PHY provider, exposing two PHYs with standard
phy_init() / phy_set_mode() / phy_power_on() operations.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
MAINTAINERS | 1 +
drivers/phy/Kconfig | 13 +++
drivers/phy/Makefile | 1 +
drivers/phy/phy-eyeq5-eth.c | 254 ++++++++++++++++++++++++++++++++++++++++++++
4 files changed, 269 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index ea72b3bd2248..3254717e59c6 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17382,6 +17382,7 @@ F: arch/mips/boot/dts/mobileye/
F: arch/mips/configs/eyeq5_defconfig
F: arch/mips/mobileye/board-epm5.its.S
F: drivers/clk/clk-eyeq.c
+F: drivers/phy/phy-eyeq5-eth.c
F: drivers/pinctrl/pinctrl-eyeq5.c
F: drivers/reset/reset-eyeq.c
F: include/dt-bindings/clock/mobileye,eyeq5-clk.h
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 678dd0452f0a..1aa6eff12dbc 100644
--- a/drivers/phy/Kconfig
+++ b/drivers/phy/Kconfig
@@ -101,6 +101,19 @@ config PHY_NXP_PTN3222
schemes. It supports all three USB 2.0 data rates: Low Speed, Full
Speed and High Speed.
+config PHY_EYEQ5_ETH
+ tristate "Ethernet PHY Driver on EyeQ5"
+ depends on OF
+ depends on MACH_EYEQ5 || COMPILE_TEST
+ select AUXILIARY_BUS
+ select GENERIC_PHY
+ default MACH_EYEQ5
+ help
+ Enable this to support the Ethernet PHY integrated on EyeQ5.
+ It supports both RGMII and SGMII. Registers are located in a
+ shared register region called OLB. If M is selected, the
+ module will be called phy-eyeq5-eth.
+
source "drivers/phy/allwinner/Kconfig"
source "drivers/phy/amlogic/Kconfig"
source "drivers/phy/broadcom/Kconfig"
diff --git a/drivers/phy/Makefile b/drivers/phy/Makefile
index bfb27fb5a494..8289497ece55 100644
--- a/drivers/phy/Makefile
+++ b/drivers/phy/Makefile
@@ -13,6 +13,7 @@ obj-$(CONFIG_PHY_SNPS_EUSB2) += phy-snps-eusb2.o
obj-$(CONFIG_USB_LGM_PHY) += phy-lgm-usb.o
obj-$(CONFIG_PHY_AIROHA_PCIE) += phy-airoha-pcie.o
obj-$(CONFIG_PHY_NXP_PTN3222) += phy-nxp-ptn3222.o
+obj-$(CONFIG_PHY_EYEQ5_ETH) += phy-eyeq5-eth.o
obj-y += allwinner/ \
amlogic/ \
broadcom/ \
diff --git a/drivers/phy/phy-eyeq5-eth.c b/drivers/phy/phy-eyeq5-eth.c
new file mode 100644
index 000000000000..b65c3d733f6c
--- /dev/null
+++ b/drivers/phy/phy-eyeq5-eth.c
@@ -0,0 +1,254 @@
+// SPDX-License-Identifier: GPL-2.0-only
+
+#include <linux/array_size.h>
+#include <linux/auxiliary_bus.h>
+#include <linux/bitfield.h>
+#include <linux/bits.h>
+#include <linux/bug.h>
+#include <linux/cleanup.h>
+#include <linux/container_of.h>
+#include <linux/device.h>
+#include <linux/err.h>
+#include <linux/errno.h>
+#include <linux/init.h>
+#include <linux/io.h>
+#include <linux/iopoll.h>
+#include <linux/lockdep.h>
+#include <linux/mod_devicetable.h>
+#include <linux/mutex.h>
+#include <linux/of.h>
+#include <linux/phy.h>
+#include <linux/phy/phy.h>
+#include <linux/slab.h>
+#include <linux/types.h>
+
+#define EQ5_PHY_COUNT 2
+
+#define EQ5_PHY0_GP 0x128
+#define EQ5_PHY1_GP 0x12c
+#define EQ5_PHY0_SGMII 0x134
+#define EQ5_PHY1_SGMII 0x138
+
+#define EQ5_GP_TX_SWRST_DIS BIT(0) // Tx SW reset
+#define EQ5_GP_TX_M_CLKE BIT(1) // Tx M clock enable
+#define EQ5_GP_SYS_SWRST_DIS BIT(2) // Sys SW reset
+#define EQ5_GP_SYS_M_CLKE BIT(3) // Sys clock enable
+#define EQ5_GP_SGMII_MODE BIT(4) // SGMII mode
+#define EQ5_GP_RGMII_DRV GENMASK(8, 5) // RGMII drive strength
+
+#define EQ5_SGMII_PWR_EN BIT(0)
+#define EQ5_SGMII_RST_DIS BIT(1)
+#define EQ5_SGMII_PLL_EN BIT(2)
+#define EQ5_SGMII_SIG_DET_SW BIT(3)
+#define EQ5_SGMII_PWR_STATE BIT(4)
+#define EQ5_SGMII_PLL_ACK BIT(18)
+#define EQ5_SGMII_PWR_STATE_ACK GENMASK(24, 20)
+
+struct eq5_phy_inst {
+ struct eq5_phy_private *priv;
+ struct phy *phy;
+ void __iomem *gp, *sgmii;
+ phy_interface_t phy_interface;
+};
+
+struct eq5_phy_private {
+ struct device *dev;
+ struct eq5_phy_inst phys[EQ5_PHY_COUNT];
+};
+
+static int eq5_phy_init(struct phy *phy)
+{
+ struct eq5_phy_inst *inst = phy_get_drvdata(phy);
+ struct eq5_phy_private *priv = inst->priv;
+ struct device *dev = priv->dev;
+ u32 reg;
+
+ dev_dbg(dev, "phy_init(inst=%ld)\n", inst - priv->phys);
+
+ writel(0, inst->gp);
+ writel(0, inst->sgmii);
+
+ udelay(5);
+
+ reg = readl(inst->gp) | EQ5_GP_TX_SWRST_DIS | EQ5_GP_TX_M_CLKE |
+ EQ5_GP_SYS_SWRST_DIS | EQ5_GP_SYS_M_CLKE |
+ FIELD_PREP(EQ5_GP_RGMII_DRV, 0x9);
+ writel(reg, inst->gp);
+
+ return 0;
+}
+
+static int eq5_phy_exit(struct phy *phy)
+{
+ struct eq5_phy_inst *inst = phy_get_drvdata(phy);
+ struct eq5_phy_private *priv = inst->priv;
+ struct device *dev = priv->dev;
+
+ dev_dbg(dev, "phy_exit(inst=%ld)\n", inst - priv->phys);
+
+ writel(0, inst->gp);
+ writel(0, inst->sgmii);
+ udelay(5);
+
+ return 0;
+}
+
+static int eq5_phy_set_mode(struct phy *phy, enum phy_mode mode, int submode)
+{
+ struct eq5_phy_inst *inst = phy_get_drvdata(phy);
+ struct eq5_phy_private *priv = inst->priv;
+ struct device *dev = priv->dev;
+
+ dev_dbg(dev, "phy_set_mode(inst=%ld, mode=%d, submode=%d)\n",
+ inst - priv->phys, mode, submode);
+
+ if (mode != PHY_MODE_ETHERNET)
+ return -EOPNOTSUPP;
+
+ if (!phy_interface_mode_is_rgmii(submode) &&
+ submode != PHY_INTERFACE_MODE_SGMII)
+ return -EOPNOTSUPP;
+
+ inst->phy_interface = submode;
+ return 0;
+}
+
+static int eq5_phy_power_on(struct phy *phy)
+{
+ struct eq5_phy_inst *inst = phy_get_drvdata(phy);
+ struct eq5_phy_private *priv = inst->priv;
+ struct device *dev = priv->dev;
+ u32 reg;
+
+ dev_dbg(dev, "phy_power_on(inst=%ld)\n", inst - priv->phys);
+
+ if (inst->phy_interface == PHY_INTERFACE_MODE_SGMII) {
+ writel(readl(inst->gp) | EQ5_GP_SGMII_MODE, inst->gp);
+
+ reg = EQ5_SGMII_PWR_EN | EQ5_SGMII_RST_DIS | EQ5_SGMII_PLL_EN;
+ writel(reg, inst->sgmii);
+
+ if (readl_poll_timeout(inst->sgmii, reg,
+ reg & EQ5_SGMII_PLL_ACK, 1, 100)) {
+ dev_err(dev, "PLL timeout\n");
+ return -ETIMEDOUT;
+ }
+
+ reg = readl(inst->sgmii);
+ reg |= EQ5_SGMII_PWR_STATE | EQ5_SGMII_SIG_DET_SW;
+ writel(reg, inst->sgmii);
+ } else {
+ writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp);
+ writel(0, inst->sgmii);
+ }
+
+ return 0;
+}
+
+static int eq5_phy_power_off(struct phy *phy)
+{
+ struct eq5_phy_inst *inst = phy_get_drvdata(phy);
+ struct eq5_phy_private *priv = inst->priv;
+ struct device *dev = priv->dev;
+
+ dev_dbg(dev, "phy_power_off(inst=%ld)\n", inst - priv->phys);
+
+ writel(readl(inst->gp) & ~EQ5_GP_SGMII_MODE, inst->gp);
+ writel(0, inst->sgmii);
+
+ return 0;
+}
+
+static const struct phy_ops eq5_phy_ops = {
+ .init = eq5_phy_init,
+ .exit = eq5_phy_exit,
+ .set_mode = eq5_phy_set_mode,
+ .power_on = eq5_phy_power_on,
+ .power_off = eq5_phy_power_off,
+};
+
+static struct phy *eq5_phy_xlate(struct device *dev,
+ const struct of_phandle_args *args)
+{
+ struct eq5_phy_private *priv = dev_get_drvdata(dev);
+
+ if (args->args_count != 1 || args->args[0] > 1)
+ return ERR_PTR(-EINVAL);
+
+ return priv->phys[args->args[0]].phy;
+}
+
+static int eq5_phy_probe_phy(struct eq5_phy_private *priv, unsigned int index,
+ void __iomem *base, unsigned int gp,
+ unsigned int sgmii)
+{
+ struct eq5_phy_inst *inst = &priv->phys[index];
+ struct device *dev = priv->dev;
+ struct phy *phy;
+
+ phy = devm_phy_create(dev, dev->of_node, &eq5_phy_ops);
+ if (IS_ERR(phy)) {
+ dev_err(dev, "failed to create PHY %u\n", index);
+ return PTR_ERR(phy);
+ }
+
+ inst->priv = priv;
+ inst->phy = phy;
+ inst->gp = base + gp;
+ inst->sgmii = base + sgmii;
+ inst->phy_interface = PHY_INTERFACE_MODE_NA;
+ phy_set_drvdata(phy, inst);
+
+ return 0;
+}
+
+static int eq5_phy_probe(struct auxiliary_device *adev,
+ const struct auxiliary_device_id *id)
+{
+ struct device *dev = &adev->dev;
+ struct phy_provider *provider;
+ struct eq5_phy_private *priv;
+ void __iomem *base;
+ int ret;
+
+ priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+ if (!priv)
+ return -ENOMEM;
+
+ priv->dev = dev;
+ dev_set_drvdata(dev, priv);
+
+ base = (void __iomem *)dev_get_platdata(dev);
+
+ ret = eq5_phy_probe_phy(priv, 0, base, EQ5_PHY0_GP, EQ5_PHY0_SGMII);
+ if (ret)
+ return ret;
+
+ ret = eq5_phy_probe_phy(priv, 1, base, EQ5_PHY1_GP, EQ5_PHY1_SGMII);
+ if (ret)
+ return ret;
+
+ provider = devm_of_phy_provider_register(dev, eq5_phy_xlate);
+ if (IS_ERR(provider)) {
+ dev_err(dev, "registering provider failed\n");
+ return PTR_ERR(provider);
+ }
+
+ return 0;
+}
+
+static const struct auxiliary_device_id eq5_phy_id_table[] = {
+ { .name = "clk_eyeq.phy" },
+ {}
+};
+MODULE_DEVICE_TABLE(auxiliary, eq5_phy_id_table);
+
+static struct auxiliary_driver eq5_phy_driver = {
+ .probe = eq5_phy_probe,
+ .id_table = eq5_phy_id_table,
+};
+module_auxiliary_driver(eq5_phy_driver);
+
+MODULE_DESCRIPTION("EyeQ5 Ethernet PHY driver");
+MODULE_AUTHOR("Théo Lebrun <theo.lebrun@bootlin.com>");
+MODULE_LICENSE("GPL");
--
2.51.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* Re: [PATCH 2/7] phy: Add driver for EyeQ5 Ethernet PHY wrapper
2025-10-22 15:39 ` [PATCH 2/7] phy: Add driver for EyeQ5 Ethernet PHY wrapper Théo Lebrun
@ 2025-10-29 15:42 ` Théo Lebrun
0 siblings, 0 replies; 10+ messages in thread
From: Théo Lebrun @ 2025-10-29 15:42 UTC (permalink / raw)
To: Théo Lebrun, Vladimir Kondratiev, Grégory Clement,
Rob Herring, Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Michael Turquette, Stephen Boyd,
Philipp Zabel, Thomas Bogendoerfer
Cc: linux-mips, devicetree, linux-kernel, linux-phy, linux-clk,
Benoît Monin, Maxime Chevallier, Tawfik Bayouk,
Thomas Petazzoni
Hello all,
On Wed Oct 22, 2025 at 5:39 PM CEST, Théo Lebrun wrote:
> EyeQ5 embeds a system-controller called OLB. It features many unrelated
> registers, and some of those are registers used to configure the
> integration of the RGMII/SGMII Cadence PHY used by MACB/GEM instances.
>
> Wrap in a neat generic PHY provider, exposing two PHYs with standard
> phy_init() / phy_set_mode() / phy_power_on() operations.
I am curious if anyone has feedback on this generic PHY driver? Patches
on MACB landed in net-next [0]. If the phy-eyeq5-eth driver approach
doesn't fly then I should sync with net land to revert MACB patches as
they are useless unless we have phy-eyeq5-eth merged.
V2 changelog at the moment (will wait a few more days before sending):
- Acked-by: Conor Dooley on dt-bindings patch.
- ptrdiff_t is printed using %td not %ld; warning on 32-bit archs [1].
[0]: https://lore.kernel.org/lkml/176166121351.2249512.7238254409117352079.git-patchwork-notify@kernel.org/
[1]: https://netdev.bots.linux.dev/static/nipa/1014126/14277857/build_32bit/stderr
Thanks!
--
Théo Lebrun, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH 3/7] clk: eyeq: use the auxiliary device creation helper
2025-10-22 15:39 [PATCH 0/7] Add generic PHY driver used by MACB/GEM on EyeQ5 Théo Lebrun
2025-10-22 15:39 ` [PATCH 1/7] dt-bindings: soc: mobileye: OLB is an Ethernet PHY provider " Théo Lebrun
2025-10-22 15:39 ` [PATCH 2/7] phy: Add driver for EyeQ5 Ethernet PHY wrapper Théo Lebrun
@ 2025-10-22 15:39 ` Théo Lebrun
2025-10-22 15:39 ` [PATCH 4/7] clk: eyeq: add EyeQ5 children auxiliary device for generic PHYs Théo Lebrun
` (3 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Théo Lebrun @ 2025-10-22 15:39 UTC (permalink / raw)
To: Vladimir Kondratiev, Grégory Clement, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Michael Turquette, Stephen Boyd,
Philipp Zabel, Thomas Bogendoerfer
Cc: linux-mips, devicetree, linux-kernel, linux-phy, linux-clk,
Benoît Monin, Maxime Chevallier, Tawfik Bayouk,
Thomas Petazzoni, Théo Lebrun, Jerome Brunet
From: Jerome Brunet <jbrunet@baylibre.com>
The auxiliary device creation of this driver is simple enough to
use the available auxiliary device creation helper.
Use it and remove some boilerplate code.
Tested-by: Théo Lebrun <theo.lebrun@bootlin.com> # On Mobileye EyeQ5
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/clk-eyeq.c | 57 +++++++++++---------------------------------------
1 file changed, 12 insertions(+), 45 deletions(-)
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index ea1c3d78e7cd..664ce7d7868d 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -322,38 +322,18 @@ static void eqc_probe_init_fixed_factors(struct device *dev,
}
}
-static void eqc_auxdev_release(struct device *dev)
-{
- struct auxiliary_device *adev = to_auxiliary_dev(dev);
-
- kfree(adev);
-}
-
-static int eqc_auxdev_create(struct device *dev, void __iomem *base,
- const char *name, u32 id)
+static void eqc_auxdev_create_optional(struct device *dev, void __iomem *base,
+ const char *name)
{
struct auxiliary_device *adev;
- int ret;
- adev = kzalloc(sizeof(*adev), GFP_KERNEL);
- if (!adev)
- return -ENOMEM;
-
- adev->name = name;
- adev->dev.parent = dev;
- adev->dev.platform_data = (void __force *)base;
- adev->dev.release = eqc_auxdev_release;
- adev->id = id;
-
- ret = auxiliary_device_init(adev);
- if (ret)
- return ret;
-
- ret = auxiliary_device_add(adev);
- if (ret)
- auxiliary_device_uninit(adev);
-
- return ret;
+ if (name) {
+ adev = devm_auxiliary_device_create(dev, name,
+ (void __force *)base);
+ if (!adev)
+ dev_warn(dev, "failed creating auxiliary device %s.%s\n",
+ KBUILD_MODNAME, name);
+ }
}
static int eqc_probe(struct platform_device *pdev)
@@ -365,7 +345,6 @@ static int eqc_probe(struct platform_device *pdev)
unsigned int i, clk_count;
struct resource *res;
void __iomem *base;
- int ret;
data = device_get_match_data(dev);
if (!data)
@@ -379,21 +358,9 @@ static int eqc_probe(struct platform_device *pdev)
if (!base)
return -ENOMEM;
- /* Init optional reset auxiliary device. */
- if (data->reset_auxdev_name) {
- ret = eqc_auxdev_create(dev, base, data->reset_auxdev_name, 0);
- if (ret)
- dev_warn(dev, "failed creating auxiliary device %s.%s: %d\n",
- KBUILD_MODNAME, data->reset_auxdev_name, ret);
- }
-
- /* Init optional pinctrl auxiliary device. */
- if (data->pinctrl_auxdev_name) {
- ret = eqc_auxdev_create(dev, base, data->pinctrl_auxdev_name, 0);
- if (ret)
- dev_warn(dev, "failed creating auxiliary device %s.%s: %d\n",
- KBUILD_MODNAME, data->pinctrl_auxdev_name, ret);
- }
+ /* Init optional auxiliary devices. */
+ eqc_auxdev_create_optional(dev, base, data->reset_auxdev_name);
+ eqc_auxdev_create_optional(dev, base, data->pinctrl_auxdev_name);
if (data->pll_count + data->div_count + data->fixed_factor_count == 0)
return 0; /* Zero clocks, we are done. */
--
2.51.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 4/7] clk: eyeq: add EyeQ5 children auxiliary device for generic PHYs
2025-10-22 15:39 [PATCH 0/7] Add generic PHY driver used by MACB/GEM on EyeQ5 Théo Lebrun
` (2 preceding siblings ...)
2025-10-22 15:39 ` [PATCH 3/7] clk: eyeq: use the auxiliary device creation helper Théo Lebrun
@ 2025-10-22 15:39 ` Théo Lebrun
2025-10-22 15:39 ` [PATCH 5/7] reset: eyeq: drop device_set_of_node_from_dev() done by parent Théo Lebrun
` (2 subsequent siblings)
6 siblings, 0 replies; 10+ messages in thread
From: Théo Lebrun @ 2025-10-22 15:39 UTC (permalink / raw)
To: Vladimir Kondratiev, Grégory Clement, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Michael Turquette, Stephen Boyd,
Philipp Zabel, Thomas Bogendoerfer
Cc: linux-mips, devicetree, linux-kernel, linux-phy, linux-clk,
Benoît Monin, Maxime Chevallier, Tawfik Bayouk,
Thomas Petazzoni, Théo Lebrun
Grow our clk-eyeq family; it knows how to spawn reset provider and pin
controller children. Expand with a generic PHY driver on EyeQ5.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
drivers/clk/clk-eyeq.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 664ce7d7868d..a9de57315e48 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -109,6 +109,7 @@ struct eqc_match_data {
const char *reset_auxdev_name;
const char *pinctrl_auxdev_name;
+ const char *eth_phy_auxdev_name;
unsigned int early_clk_count;
};
@@ -361,6 +362,7 @@ static int eqc_probe(struct platform_device *pdev)
/* Init optional auxiliary devices. */
eqc_auxdev_create_optional(dev, base, data->reset_auxdev_name);
eqc_auxdev_create_optional(dev, base, data->pinctrl_auxdev_name);
+ eqc_auxdev_create_optional(dev, base, data->eth_phy_auxdev_name);
if (data->pll_count + data->div_count + data->fixed_factor_count == 0)
return 0; /* Zero clocks, we are done. */
@@ -521,6 +523,7 @@ static const struct eqc_match_data eqc_eyeq5_match_data = {
.reset_auxdev_name = "reset",
.pinctrl_auxdev_name = "pinctrl",
+ .eth_phy_auxdev_name = "phy",
.early_clk_count = ARRAY_SIZE(eqc_eyeq5_early_plls) +
ARRAY_SIZE(eqc_eyeq5_early_fixed_factors),
--
2.51.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 5/7] reset: eyeq: drop device_set_of_node_from_dev() done by parent
2025-10-22 15:39 [PATCH 0/7] Add generic PHY driver used by MACB/GEM on EyeQ5 Théo Lebrun
` (3 preceding siblings ...)
2025-10-22 15:39 ` [PATCH 4/7] clk: eyeq: add EyeQ5 children auxiliary device for generic PHYs Théo Lebrun
@ 2025-10-22 15:39 ` Théo Lebrun
2025-10-22 15:39 ` [PATCH 6/7] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers Théo Lebrun
2025-10-22 15:39 ` [PATCH 7/7] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs Théo Lebrun
6 siblings, 0 replies; 10+ messages in thread
From: Théo Lebrun @ 2025-10-22 15:39 UTC (permalink / raw)
To: Vladimir Kondratiev, Grégory Clement, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Michael Turquette, Stephen Boyd,
Philipp Zabel, Thomas Bogendoerfer
Cc: linux-mips, devicetree, linux-kernel, linux-phy, linux-clk,
Benoît Monin, Maxime Chevallier, Tawfik Bayouk,
Thomas Petazzoni, Théo Lebrun, Jerome Brunet
Our parent driver (clk-eyeq) now does the
device_set_of_node_from_dev(dev, dev->parent)
call through the newly introduced devm_auxiliary_device_create() helper.
Doing it again in the reset-eyeq probe would be redundant.
Drop both the WARN_ON() and the device_set_of_node_from_dev() call.
Also fix the following comment that talks about "our newfound OF node".
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/reset/reset-eyeq.c | 24 ++----------------------
1 file changed, 2 insertions(+), 22 deletions(-)
diff --git a/drivers/reset/reset-eyeq.c b/drivers/reset/reset-eyeq.c
index 2d3998368a1c..8018fa895427 100644
--- a/drivers/reset/reset-eyeq.c
+++ b/drivers/reset/reset-eyeq.c
@@ -410,13 +410,6 @@ static int eqr_of_xlate_twocells(struct reset_controller_dev *rcdev,
return eqr_of_xlate_internal(rcdev, reset_spec->args[0], reset_spec->args[1]);
}
-static void eqr_of_node_put(void *_dev)
-{
- struct device *dev = _dev;
-
- of_node_put(dev->of_node);
-}
-
static int eqr_probe(struct auxiliary_device *adev,
const struct auxiliary_device_id *id)
{
@@ -427,21 +420,8 @@ static int eqr_probe(struct auxiliary_device *adev,
int ret;
/*
- * We are an auxiliary device of clk-eyeq. We do not have an OF node by
- * default; let's reuse our parent's OF node.
- */
- WARN_ON(dev->of_node);
- device_set_of_node_from_dev(dev, dev->parent);
- if (!dev->of_node)
- return -ENODEV;
-
- ret = devm_add_action_or_reset(dev, eqr_of_node_put, dev);
- if (ret)
- return ret;
-
- /*
- * Using our newfound OF node, we can get match data. We cannot use
- * device_get_match_data() because it does not match reused OF nodes.
+ * Get match data. We cannot use device_get_match_data() because it does
+ * not accept reused OF nodes; see device_set_of_node_from_dev().
*/
match = of_match_node(dev->driver->of_match_table, dev->of_node);
if (!match || !match->data)
--
2.51.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 6/7] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers
2025-10-22 15:39 [PATCH 0/7] Add generic PHY driver used by MACB/GEM on EyeQ5 Théo Lebrun
` (4 preceding siblings ...)
2025-10-22 15:39 ` [PATCH 5/7] reset: eyeq: drop device_set_of_node_from_dev() done by parent Théo Lebrun
@ 2025-10-22 15:39 ` Théo Lebrun
2025-10-22 15:39 ` [PATCH 7/7] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs Théo Lebrun
6 siblings, 0 replies; 10+ messages in thread
From: Théo Lebrun @ 2025-10-22 15:39 UTC (permalink / raw)
To: Vladimir Kondratiev, Grégory Clement, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Michael Turquette, Stephen Boyd,
Philipp Zabel, Thomas Bogendoerfer
Cc: linux-mips, devicetree, linux-kernel, linux-phy, linux-clk,
Benoît Monin, Maxime Chevallier, Tawfik Bayouk,
Thomas Petazzoni, Théo Lebrun
Add both MACB/GEM instances found in the Mobileye EyeQ5 SoC.
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
arch/mips/boot/dts/mobileye/eyeq5.dtsi | 45 ++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq5.dtsi b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
index 36a73e8a63a1..cec5ad875228 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5.dtsi
+++ b/arch/mips/boot/dts/mobileye/eyeq5.dtsi
@@ -77,6 +77,8 @@ aliases {
serial0 = &uart0;
serial1 = &uart1;
serial2 = &uart2;
+ ethernet0 = &macb0;
+ ethernet1 = &macb1;
};
cpu_intc: interrupt-controller {
@@ -231,6 +233,7 @@ olb: system-controller@e00000 {
#clock-cells = <1>;
clocks = <&xtal>;
clock-names = "ref";
+ #phy-cells = <1>;
};
gic: interrupt-controller@140000 {
@@ -305,6 +308,48 @@ gpio1: gpio@1500000 {
#interrupt-cells = <2>;
resets = <&olb 0 26>;
};
+
+ iocu-bus {
+ compatible = "simple-bus";
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges;
+ dma-coherent;
+ dma-ranges = <0x10 0x00000000 0x0 0x0 0x10 0>;
+
+ macb0: ethernet@2a00000 {
+ compatible = "mobileye,eyeq5-gem";
+ reg = <0x0 0x02a00000 0x0 0x4000>;
+ interrupt-parent = <&gic>;
+ /* One interrupt per queue */
+ interrupts = <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 23 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "pclk", "hclk", "tsu_clk";
+ clocks = <&pclk>, <&pclk>, <&tsu_clk>;
+ nvmem-cells = <ð0_mac>;
+ nvmem-cell-names = "mac-address";
+ phys = <&olb 0>;
+ };
+
+ macb1: ethernet@2b00000 {
+ compatible = "mobileye,eyeq5-gem";
+ reg = <0x0 0x02b00000 0x0 0x4000>;
+ interrupt-parent = <&gic>;
+ /* One interrupt per queue */
+ interrupts = <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SHARED 24 IRQ_TYPE_LEVEL_HIGH>;
+ clock-names = "pclk", "hclk", "tsu_clk";
+ clocks = <&pclk>, <&pclk>, <&tsu_clk>;
+ nvmem-cells = <ð1_mac>;
+ nvmem-cell-names = "mac-address";
+ phys = <&olb 1>;
+ };
+ };
+
};
};
--
2.51.1
^ permalink raw reply related [flat|nested] 10+ messages in thread* [PATCH 7/7] MIPS: mobileye: eyeq5-epm: add two Cadence GEM Ethernet PHYs
2025-10-22 15:39 [PATCH 0/7] Add generic PHY driver used by MACB/GEM on EyeQ5 Théo Lebrun
` (5 preceding siblings ...)
2025-10-22 15:39 ` [PATCH 6/7] MIPS: mobileye: eyeq5: add two Cadence GEM Ethernet controllers Théo Lebrun
@ 2025-10-22 15:39 ` Théo Lebrun
6 siblings, 0 replies; 10+ messages in thread
From: Théo Lebrun @ 2025-10-22 15:39 UTC (permalink / raw)
To: Vladimir Kondratiev, Grégory Clement, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Vinod Koul,
Kishon Vijay Abraham I, Michael Turquette, Stephen Boyd,
Philipp Zabel, Thomas Bogendoerfer
Cc: linux-mips, devicetree, linux-kernel, linux-phy, linux-clk,
Benoît Monin, Maxime Chevallier, Tawfik Bayouk,
Thomas Petazzoni, Théo Lebrun, Andrew Lunn
The Mobileye EyeQ5 eval board (EPM) embeds two MDIO PHYs.
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Théo Lebrun <theo.lebrun@bootlin.com>
---
arch/mips/boot/dts/mobileye/eyeq5-epm5.dts | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
index 9fc1a1b0a81b..babf52731ea6 100644
--- a/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
+++ b/arch/mips/boot/dts/mobileye/eyeq5-epm5.dts
@@ -29,3 +29,29 @@ temperature-sensor@48 {
label = "U60";
};
};
+
+&macb0 {
+ phy-mode = "sgmii";
+ phy-handle = <&macb0_phy>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ macb0_phy: ethernet-phy@e {
+ reg = <0xe>;
+ };
+ };
+};
+
+&macb1 {
+ phy-mode = "rgmii-id";
+ phy-handle = <&macb1_phy>;
+
+ mdio {
+ #address-cells = <1>;
+ #size-cells = <0>;
+ macb1_phy: ethernet-phy@e {
+ reg = <0xe>;
+ };
+ };
+};
--
2.51.1
^ permalink raw reply related [flat|nested] 10+ messages in thread