[PATCH 00/13] Introducing the Mobileye EyeQ6Lplus SoC

[PATCH 00/13] Introducing the Mobileye EyeQ6Lplus SoC

[Benoît Monin]

The Eyeq6Lplus is a new system-on-chip part of Mobileye's EyeQ family
of SoC aimed at Advanced Driver Assistance Systems (ADAS). It is built
around a multicore MIPS I6500 with 2 cores and 8 threads and integrates
controllers and accelerators dedicated to driving assistance.

This patchset adds the initial support for the EyeQ6Lplus and its
evaluation board with the following list of controllers:
* The OLB ("Other Logic Block") providing clocks, resets and pin controls.
* One UART from DesignWare.
* One GPIO controller from DesignWare.
* Two SPI controllers from DesignWare, one in host mode and one in target
  mode.
* One octoSPI flash controller from Cadence, identical to the one found
  in the EyeQ5.
* Two I2C controllers from Designware.

The support for the particularities of the I2C controllers is 
currently under review[1], but basic operations (single read,
single write, write-then-read) work with the compatible fallback to
"snps,designware-i2c".

The patch series adds the device tree bindings for the SoC and the OLB. It
also adds the Kconfig entry for the EyeQ6Lplus, the SoC and evaluation
board device tree, and the defconfig. For the OLB, the series adds the
match data to the clk-eyeq, reset-eyeq and pinctrl-eyeq5 drivers.

It also brings three other changes. One for the pinctrl-eyeq5 driver to
access the pin descriptions, pin functions and pin bank register via
the match data instead of directly. This is needed to add support for
the EyeQ6Lplus alongside the EyeQ5 to the pinctrl driver.

To be able to match against compatible entries, An OF node is needed
but the pinctrl-eyeq5 does not have one as it is an auxiliary device
of clk-eyeq. As part of his MACB phy series[2], Théo switched to
devm_auxiliary_device_create() to register the auxiliary devices and this
helper sets the OF node of the auxiliary device. To avoid a dependency
between the patch series, eq5p_probe() is able to handle both cases,
having the of_node field already set in the device structure or getting
it from the parent device. After both series are merged, a cleanup of
the pinctrl-eyeq5 probe function can be done.

The two other changes are in the clk-eyeq driver. First we skip the
post-divisor when computing the PLL frequency in the clk-eyeq driver,
to match how the clock signal is wired internally in all EyeQ PLL and
compute the correct frequency for the PLL of the EyeQ6Lplus. Second we
adjust the accuracy and down spreading computation of the PLL frequency
as the spread spectrum of all EyeQ PLL is in 1/1024 and not in 1/1000
as previously thought.

[1]: https://lore.kernel.org/all/20251126-i2c-dw-v4-0-b0654598e7c5@bootlin.com/
[2]: https://lore.kernel.org/all/20251215-macb-phy-v5-0-a9dfea39da34@bootlin.com/

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
Benoît Monin (13):
      dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC
      dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB
      MIPS: Add Mobileye eyeQ6Lplus support
      reset: eyeq: Add Mobileye EyeQ6Lplus OLB
      pinctrl: eyeq5: Use match data
      pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB
      clk: eyeq: Skip post-divisor when computing PLL frequency
      clk: eyeq: Adjust PLL accuracy computation
      clk: eyeq: Add Mobileye EyeQ6Lplus OLB
      MIPS: Add Mobileye EyeQ6Lplus SoC dtsi
      MIPS: Add Mobileye EyeQ6Lplus evaluation board dts
      MIPS: config: add eyeq6lplus_defconfig
      MAINTAINERS: Mobileye: Add EyeQ6Lplus files

 .../devicetree/bindings/mips/mobileye.yaml         |   5 +
 .../soc/mobileye/mobileye,eyeq6lplus-olb.yaml      | 208 ++++++++++
 MAINTAINERS                                        |   4 +-
 arch/mips/boot/dts/mobileye/Makefile               |   1 +
 arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts    | 112 +++++
 arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi   |  84 ++++
 arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi        | 169 ++++++++
 arch/mips/configs/eyeq6lplus_defconfig             | 119 ++++++
 arch/mips/mobileye/Kconfig                         |   3 +
 arch/mips/mobileye/Platform                        |   1 +
 drivers/clk/Kconfig                                |   4 +-
 drivers/clk/clk-eyeq.c                             |  90 +++-
 drivers/pinctrl/Kconfig                            |   4 +-
 drivers/pinctrl/pinctrl-eyeq5.c                    | 462 +++++++++++++++------
 drivers/reset/Kconfig                              |   4 +-
 drivers/reset/reset-eyeq.c                         |  31 ++
 .../dt-bindings/clock/mobileye,eyeq6lplus-clk.h    |  37 ++
 17 files changed, 1192 insertions(+), 146 deletions(-)
---
base-commit: 8f0b4cce4481fb22653697cced8d0d04027cb1e8
change-id: 20251128-eyeq6lplus-961c630f0940

Best regards,
-- 
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[PATCH 01/13] dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC

[Benoît Monin]

Add an entry to the mobileye bindings for the EyeQ6Lplus
which is part of the EyeQ family of system-on-chip.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 Documentation/devicetree/bindings/mips/mobileye.yaml | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/mips/mobileye.yaml b/Documentation/devicetree/bindings/mips/mobileye.yaml
index d60744550e46..83abe268e96b 100644
--- a/Documentation/devicetree/bindings/mips/mobileye.yaml
+++ b/Documentation/devicetree/bindings/mips/mobileye.yaml
@@ -31,6 +31,11 @@ properties:
           - enum:
               - mobileye,eyeq6h-epm6
           - const: mobileye,eyeq6h
+      - description: Boards with Mobileye EyeQ6Lplus SoC
+        items:
+          - enum:
+              - mobileye,eyeq6lplus-epm6
+          - const: mobileye,eyeq6lplus
 
 additionalProperties: true
 

-- 
2.52.0

Re: [PATCH 01/13] dt-bindings: mips: Add Mobileye EyeQ6Lplus SoC

[Rob Herring (Arm)]

On Wed, 17 Dec 2025 14:35:51 +0100, Benoît Monin wrote:
> Add an entry to the mobileye bindings for the EyeQ6Lplus
> which is part of the EyeQ family of system-on-chip.
> 
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  Documentation/devicetree/bindings/mips/mobileye.yaml | 5 +++++
>  1 file changed, 5 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH 02/13] dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB

[Benoît Monin]

The "Other Logic Block" found in the EyeQ6Lplus from Mobileye provides
various functions for the controllers present in the SoC.

The OLB produces 22 clocks derived from its input, which is connected
to the main oscillator of the SoC.

It provides reset signals via two reset domains.

It also controls 32 pins to be either a GPIO or an alternate function.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 .../soc/mobileye/mobileye,eyeq6lplus-olb.yaml      | 208 +++++++++++++++++++++
 .../dt-bindings/clock/mobileye,eyeq6lplus-clk.h    |  37 ++++
 2 files changed, 245 insertions(+)

diff --git a/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq6lplus-olb.yaml b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq6lplus-olb.yaml
new file mode 100644
index 000000000000..8334876cf4e6
--- /dev/null
+++ b/Documentation/devicetree/bindings/soc/mobileye/mobileye,eyeq6lplus-olb.yaml
@@ -0,0 +1,208 @@
+# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/soc/mobileye/mobileye,eyeq6lplus-olb.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Mobileye EyeQ6Lplus SoC system controller
+
+maintainers:
+  - Benoît Monin <benoit.monin@bootlin.com>
+  - Grégory Clement <gregory.clement@bootlin.com>
+  - Théo Lebrun <theo.lebrun@bootlin.com>
+  - Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
+
+description:
+  OLB ("Other Logic Block") is a hardware block grouping smaller blocks.
+  Clocks, resets, pinctrl are being handled from here. EyeQ6Lplus hosts
+  a single instance providing 22 clocks, two reset domains and one bank
+  of 32 pins.
+
+properties:
+  compatible:
+    items:
+      - const: mobileye,eyeq6lplus-olb
+      - const: syscon
+
+  reg:
+    maxItems: 1
+
+  '#reset-cells':
+    description:
+      First cell is reset domain index.
+      Second cell is reset index inside that domain.
+    const: 2
+
+  '#clock-cells':
+    const: 1
+
+  clocks:
+    maxItems: 1
+    description:
+      Input parent clock to all PLLs. Expected to be the main crystal.
+
+  clock-names:
+    const: ref
+
+patternProperties:
+  '-pins?$':
+    type: object
+    description: Pin muxing configuration.
+    $ref: /schemas/pinctrl/pinmux-node.yaml#
+    additionalProperties: false
+    properties:
+      pins: true
+      function:
+        enum: [gpio, timer0, timer1, uart_ssi, spi0, uart0, timer2, timer3,
+               timer_ext0, spi1, timer_ext1, ext_ref_clk, mipi_ref_clk]
+      bias-disable: true
+      bias-pull-down: true
+      bias-pull-up: true
+      drive-strength: true
+    required:
+      - pins
+      - function
+    allOf:
+      - if:
+          properties:
+            function:
+              const: gpio
+        then:
+          properties:
+            pins:
+              items: # PA0 - PA31
+                pattern: '^(PA[1,2]?[0-9]|PA3[0,1])$'
+      - if:
+          properties:
+            function:
+              const: timer0
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA0, PA1]
+      - if:
+          properties:
+            function:
+              const: timer1
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA2, PA3]
+      - if:
+          properties:
+            function:
+              const: uart_ssi
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA4, PA5]
+      - if:
+          properties:
+            function:
+              const: spi0
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA6, PA7, PA8, PA9, PA10]
+      - if:
+          properties:
+            function:
+              const: uart0
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA11, PA12]
+      - if:
+          properties:
+            function:
+              const: timer2
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA13, PA14]
+      - if:
+          properties:
+            function:
+              const: timer3
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA15, PA16]
+      - if:
+          properties:
+            function:
+              const: timer_ext0
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA17, PA18, PA19, PA20]
+      - if:
+          properties:
+            function:
+              const: spi1
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA21, PA22, PA23, PA24, PA25]
+      - if:
+          properties:
+            function:
+              const: timer_ext1
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA26, PA27, PA28, PA29]
+      - if:
+          properties:
+            function:
+              const: ext_ref_clk
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA30]
+      - if:
+          properties:
+            function:
+              const: mipi_ref_clk
+        then:
+          properties:
+            pins:
+              items:
+                enum: [PA31]
+
+required:
+  - compatible
+  - reg
+  - '#clock-cells'
+  - clocks
+  - clock-names
+  - '#reset-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+    soc {
+      #address-cells = <2>;
+      #size-cells = <2>;
+
+      system-controller@e8400000 {
+        compatible = "mobileye,eyeq6lplus-olb", "syscon";
+        reg = <0 0xe8400000 0x0 0x80000>;
+        #reset-cells = <2>;
+        #clock-cells = <1>;
+        clocks = <&xtal>;
+        clock-names = "ref";
+      };
+    };
diff --git a/include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h b/include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h
new file mode 100644
index 000000000000..20d84ee24ad5
--- /dev/null
+++ b/include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h
@@ -0,0 +1,37 @@
+/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
+/*
+ * Copyright (C) 2025 Mobileye Vision Technologies Ltd.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ6LPLUS_CLK_H
+#define _DT_BINDINGS_CLOCK_MOBILEYE_EYEQ6LPLUS_CLK_H
+
+#define EQ6LPC_PLL_CPU		0
+#define EQ6LPC_PLL_DDR		1
+#define EQ6LPC_PLL_PER		2
+#define EQ6LPC_PLL_VDI		3
+#define EQ6LPC_PLL_ACC		4
+
+#define EQ6LPC_CPU_OCC		5
+
+#define EQ6LPC_ACC_VDI		6
+#define EQ6LPC_ACC_OCC		7
+#define EQ6LPC_ACC_FCMU		8
+
+#define EQ6LPC_DDR_OCC		9
+
+#define EQ6LPC_PER_OCC		10
+#define EQ6LPC_PER_I2C_SER	11
+#define EQ6LPC_PER_PCLK		12
+#define EQ6LPC_PER_TSU		13
+#define EQ6LPC_PER_OSPI		14
+#define EQ6LPC_PER_GPIO		15
+#define EQ6LPC_PER_TIMER	16
+#define EQ6LPC_PER_I2C		17
+#define EQ6LPC_PER_UART		18
+#define EQ6LPC_PER_SPI		19
+#define EQ6LPC_PER_PERIPH	20
+
+#define EQ6LPC_VDI_OCC		21
+
+#endif

-- 
2.52.0

Re: [PATCH 02/13] dt-bindings: soc: mobileye: Add EyeQ6Lplus OLB

[Rob Herring (Arm)]

On Wed, 17 Dec 2025 14:35:52 +0100, Benoît Monin wrote:
> The "Other Logic Block" found in the EyeQ6Lplus from Mobileye provides
> various functions for the controllers present in the SoC.
> 
> The OLB produces 22 clocks derived from its input, which is connected
> to the main oscillator of the SoC.
> 
> It provides reset signals via two reset domains.
> 
> It also controls 32 pins to be either a GPIO or an alternate function.
> 
> Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
> ---
>  .../soc/mobileye/mobileye,eyeq6lplus-olb.yaml      | 208 +++++++++++++++++++++
>  .../dt-bindings/clock/mobileye,eyeq6lplus-clk.h    |  37 ++++
>  2 files changed, 245 insertions(+)
> 

Reviewed-by: Rob Herring (Arm) <robh@kernel.org>

[PATCH 03/13] MIPS: Add Mobileye eyeQ6Lplus support

[Benoît Monin]

Add the EyeQ6Lplus to the group of choices for Mobileye SoC
and set the kernel load address specific to this SoC.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 arch/mips/mobileye/Kconfig  | 3 +++
 arch/mips/mobileye/Platform | 1 +
 2 files changed, 4 insertions(+)

diff --git a/arch/mips/mobileye/Kconfig b/arch/mips/mobileye/Kconfig
index f9abb2d6e178..8a4868d2e28f 100644
--- a/arch/mips/mobileye/Kconfig
+++ b/arch/mips/mobileye/Kconfig
@@ -12,6 +12,9 @@ choice
 
 	config MACH_EYEQ6H
 		bool "Mobileye EyeQ6H SoC"
+
+	config MACH_EYEQ6LPLUS
+		bool "Mobileye EyeQ6Lplus SoC"
 endchoice
 
 config FIT_IMAGE_FDT_EPM5
diff --git a/arch/mips/mobileye/Platform b/arch/mips/mobileye/Platform
index 69f775bbbb1e..93b533492b58 100644
--- a/arch/mips/mobileye/Platform
+++ b/arch/mips/mobileye/Platform
@@ -10,6 +10,7 @@
 
 load-$(CONFIG_MACH_EYEQ5)	= 0xa800000808000000
 load-$(CONFIG_MACH_EYEQ6H)	= 0xa800000100800000
+load-$(CONFIG_MACH_EYEQ6LPLUS)	= 0xa800000108800000
 all-$(CONFIG_MACH_EYEQ5)	+= vmlinux.gz.itb
 
 its-y					:= vmlinux.its.S

-- 
2.52.0

[PATCH 04/13] reset: eyeq: Add Mobileye EyeQ6Lplus OLB

[Benoît Monin]

Declare the two reset domains found in the EyeQ6Lplus OLB and add
them to the data matched by 'mobileye,eyeq6lplus-olb' compatible.

Those reset domains are identical to those present in the EyeQ5
OLB, so no changes are needed to support them.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/reset/Kconfig      |  4 ++--
 drivers/reset/reset-eyeq.c | 31 +++++++++++++++++++++++++++++++
 2 files changed, 33 insertions(+), 2 deletions(-)

diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig
index 6e5d6deffa7d..ba0814f0f292 100644
--- a/drivers/reset/Kconfig
+++ b/drivers/reset/Kconfig
@@ -85,9 +85,9 @@ config RESET_EIC7700
 
 config RESET_EYEQ
 	bool "Mobileye EyeQ reset controller"
-	depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
+	depends on MACH_EYEQ5 || MACH_EYEQ6H || MACH_EYEQ6LPLUS || COMPILE_TEST
 	select AUXILIARY_BUS
-	default MACH_EYEQ5 || MACH_EYEQ6H
+	default MACH_EYEQ5 || MACH_EYEQ6H || MACH_EYEQ6LPLUS
 	help
 	  This enables the Mobileye EyeQ reset controller, used in EyeQ5, EyeQ6L
 	  and EyeQ6H SoCs.
diff --git a/drivers/reset/reset-eyeq.c b/drivers/reset/reset-eyeq.c
index 2d3998368a1c..791b7283111e 100644
--- a/drivers/reset/reset-eyeq.c
+++ b/drivers/reset/reset-eyeq.c
@@ -49,6 +49,18 @@
  *  8. MPC0	 9. MPC1	10. MPC2	11. MPC3
  * 12. MPC4
  *
+ * Known resets in EyeQ6Lplus domain 0 (type EQR_EYEQ5_PCIE):
+ *  0. SPI0	 1. SPI1	 2. UART0	 3. I2C0
+ *  4. I2C1	 5. TIMER0	 6. TIMER1	 7. TIMER2
+ *  8. TIMER3	 9. WD0		10. WD1		11. EXT0
+ * 12. EXT1	13. GPIO
+ *
+ * Known resets in EyeQ6Lplus domain 1 (type EQR_EYEQ5_ACRP):
+ *  0. VMP0	 1. VMP1	 2. VMP2	 3. VMP3
+ *  4. PMA0	 5. PMA1	 6. PMAC0	 7. PMAC1
+ *  8. MPC0	 9. MPC1	10. MPC2	11. MPC3
+ * 12. MPC4
+ *
  * Known resets in EyeQ6H west/east (type EQR_EYEQ6H_SARCR):
  *  0. CAN	 1. SPI0	 2. SPI1	 3. UART0
  *  4. UART1	 5. I2C0	 6. I2C1	 7. -hole-
@@ -521,6 +533,24 @@ static const struct eqr_match_data eqr_eyeq6l_data = {
 	.domains	= eqr_eyeq6l_domains,
 };
 
+static const struct eqr_domain_descriptor eqr_eyeq6lplus_domains[] = {
+	{
+		.type = EQR_EYEQ5_PCIE,
+		.valid_mask = 0x3FFF,
+		.offset = 0x004,
+	},
+	{
+		.type = EQR_EYEQ5_ACRP,
+		.valid_mask = 0x00FF,
+		.offset = 0x200,
+	},
+};
+
+static const struct eqr_match_data eqr_eyeq6lplus_data = {
+	.domain_count	= ARRAY_SIZE(eqr_eyeq6lplus_domains),
+	.domains	= eqr_eyeq6lplus_domains,
+};
+
 /* West and east OLBs each have an instance. */
 static const struct eqr_domain_descriptor eqr_eyeq6h_we_domains[] = {
 	{
@@ -555,6 +585,7 @@ static const struct eqr_match_data eqr_eyeq6h_acc_data = {
 static const struct of_device_id eqr_match_table[] = {
 	{ .compatible = "mobileye,eyeq5-olb", .data = &eqr_eyeq5_data },
 	{ .compatible = "mobileye,eyeq6l-olb", .data = &eqr_eyeq6l_data },
+	{ .compatible = "mobileye,eyeq6lplus-olb", .data = &eqr_eyeq6lplus_data },
 	{ .compatible = "mobileye,eyeq6h-west-olb", .data = &eqr_eyeq6h_we_data },
 	{ .compatible = "mobileye,eyeq6h-east-olb", .data = &eqr_eyeq6h_we_data },
 	{ .compatible = "mobileye,eyeq6h-acc-olb", .data = &eqr_eyeq6h_acc_data },

-- 
2.52.0

[PATCH 05/13] pinctrl: eyeq5: Use match data

[Benoît Monin]

Instead of using the pin descriptions, pin functions and register offsets
of the EyeQ5 directly, access those via a pointer to a newly introduced
struct eq5p_match_data.

This structure contains, in addition to the pin descriptions and pin
functions, an array of pin banks. Each bank holds the number of pins
and the register offsets.

All functions accessing a pin now use a pointer to a bank structure and
an offset inside that bank. The conversion from a pin number to a bank
and an offset is done in the new function eq5p_pin_to_bank_offset(),
which replace eq5p_pin_to_bank() and eq5p_pin_to_offset().

All the data related to the EyeQ5 is declared with the eq5p_eyeq5_
prefix to distinguish it from the common code.

During the probe, we now get a reference to the parent OF node if we
don't already have it and use that node to get the match data. We cannot
directly use an OF node since pinctrl-eyeq5 is an auxiliary device
of clk-eyeq.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/pinctrl/pinctrl-eyeq5.c | 367 ++++++++++++++++++++++++++--------------
 1 file changed, 239 insertions(+), 128 deletions(-)

diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq5.c
index 5f6af934a516..e48add1d965d 100644
--- a/drivers/pinctrl/pinctrl-eyeq5.c
+++ b/drivers/pinctrl/pinctrl-eyeq5.c
@@ -26,6 +26,7 @@
 #include <linux/errno.h>
 #include <linux/io.h>
 #include <linux/mod_devicetable.h>
+#include <linux/of.h>
 #include <linux/seq_file.h>
 #include <linux/slab.h>
 #include <linux/types.h>
@@ -38,18 +39,6 @@
 #include "core.h"
 #include "pinctrl-utils.h"
 
-struct eq5p_pinctrl {
-	struct pinctrl_desc	desc;
-	void __iomem		*base;
-};
-
-enum eq5p_bank {
-	EQ5P_BANK_A,
-	EQ5P_BANK_B,
-
-	EQ5P_BANK_COUNT,
-};
-
 enum eq5p_regs {
 	EQ5P_PD,
 	EQ5P_PU,
@@ -60,9 +49,24 @@ enum eq5p_regs {
 	EQ5P_REG_COUNT,
 };
 
-static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] = {
-	[EQ5P_BANK_A] = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},
-	[EQ5P_BANK_B] = {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4},
+struct eq5p_bank {
+	const unsigned int npins;
+	const unsigned int regs[EQ5P_REG_COUNT];
+};
+
+struct eq5p_match_data {
+	const unsigned int npins;
+	const unsigned int nfunctions;
+	const unsigned int nbanks;
+	const struct pinctrl_pin_desc *pins;
+	const struct pinfunction *functions;
+	const struct eq5p_bank *banks;
+};
+
+struct eq5p_pinctrl {
+	struct pinctrl_desc		desc;
+	void __iomem			*base;
+	const struct eq5p_match_data	*data;
 };
 
 /*
@@ -70,10 +74,18 @@ static const unsigned int eq5p_regs[EQ5P_BANK_COUNT][EQ5P_REG_COUNT] = {
  */
 #define EQ5P_DS_MASK	GENMASK(1, 0)
 
+/*
+ * The GPIO function is always the first function
+ */
+#define EQ5P_GPIO_FUNC_SELECTOR 0
+
+/* Helper to declare pinfunction */
+#define EQ5P_PINFUNCTION(func, groups) PINCTRL_PINFUNCTION(func, groups, ARRAY_SIZE(groups))
+
 /*
  * Comments to the right of each pin are the "signal name" in the datasheet.
  */
-static const struct pinctrl_pin_desc eq5p_pins[] = {
+static const struct pinctrl_pin_desc eq5p_eyeq5_pins[] = {
 	/* Bank A */
 	PINCTRL_PIN(0,  "PA0"),  /* A0_TIMER0_CK */
 	PINCTRL_PIN(1,  "PA1"),  /* A1_TIMER0_EOC */
@@ -105,35 +117,35 @@ static const struct pinctrl_pin_desc eq5p_pins[] = {
 	PINCTRL_PIN(27, "PA27"), /* A27_SPI_1_CS1 */
 	PINCTRL_PIN(28, "PA28"), /* A28_REF_CLK0 */
 
-#define EQ5P_PIN_OFFSET_BANK_B	29
+#define EQ5P_EYEQ5_PIN_OFFSET_BANK_B	29
 
 	/* Bank B */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 0,  "PB0"),  /* B0_TIMER3_CK */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 1,  "PB1"),  /* B1_TIMER3_EOC */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 2,  "PB2"),  /* B2_TIMER4_CK */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 3,  "PB3"),  /* B3_TIMER4_EOC */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 4,  "PB4"),  /* B4_TIMER6_EXT_INCAP1 */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 5,  "PB5"),  /* B5_TIMER6_EXT_INCAP2 */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 6,  "PB6"),  /* B6_TIMER6_EXT_OUTCMP1 */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 7,  "PB7"),  /* B7_TIMER6_EXT_OUTCMP2 */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 8,  "PB8"),  /* B8_UART_2_TX */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 9,  "PB9"),  /* B9_UART_2_RX */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 */
-	PINCTRL_PIN(EQ5P_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 0,  "PB0"),  /* B0_TIMER3_CK */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 1,  "PB1"),  /* B1_TIMER3_EOC */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 2,  "PB2"),  /* B2_TIMER4_CK */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 3,  "PB3"),  /* B3_TIMER4_EOC */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 4,  "PB4"),  /* B4_TIMER6_EXT_INCAP1 */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 5,  "PB5"),  /* B5_TIMER6_EXT_INCAP2 */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 6,  "PB6"),  /* B6_TIMER6_EXT_OUTCMP1 */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 7,  "PB7"),  /* B7_TIMER6_EXT_OUTCMP2 */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 8,  "PB8"),  /* B8_UART_2_TX */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 9,  "PB9"),  /* B9_UART_2_RX */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 10, "PB10"), /* B10_CAN_2_TX */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 11, "PB11"), /* B11_CAN_2_RX */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 12, "PB12"), /* B12_SPI_2_DO */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 13, "PB13"), /* B13_SPI_2_DI */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 14, "PB14"), /* B14_SPI_2_CK */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 15, "PB15"), /* B15_SPI_2_CS0 */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 16, "PB16"), /* B16_SPI_2_CS1 */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 17, "PB17"), /* B17_SPI_3_DO */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 18, "PB18"), /* B18_SPI_3_DI */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 19, "PB19"), /* B19_SPI_3_CK */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 20, "PB20"), /* B20_SPI_3_CS0 */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 21, "PB21"), /* B21_SPI_3_CS1 */
+	PINCTRL_PIN(EQ5P_EYEQ5_PIN_OFFSET_BANK_B + 22, "PB22"), /* B22_MCLK0 */
 };
 
-static const char * const gpio_groups[] = {
+static const char * const eq5p_eyeq5_gpio_groups[] = {
 	/* Bank A */
 	"PA0",  "PA1",  "PA2",  "PA3",  "PA4",  "PA5",  "PA6",  "PA7",
 	"PA8",  "PA9",  "PA10", "PA11", "PA12", "PA13", "PA14", "PA15",
@@ -147,70 +159,90 @@ static const char * const gpio_groups[] = {
 };
 
 /* Groups of functions on bank A */
-static const char * const timer0_groups[] = { "PA0", "PA1" };
-static const char * const timer1_groups[] = { "PA2", "PA3" };
-static const char * const timer2_groups[] = { "PA4", "PA5" };
-static const char * const timer5_groups[] = { "PA6", "PA7", "PA8", "PA9" };
-static const char * const uart0_groups[] = { "PA10", "PA11" };
-static const char * const uart1_groups[] = { "PA12", "PA13" };
-static const char * const can0_groups[] = { "PA14", "PA15" };
-static const char * const can1_groups[] = { "PA16", "PA17" };
-static const char * const spi0_groups[] = { "PA18", "PA19", "PA20", "PA21", "PA22" };
-static const char * const spi1_groups[] = { "PA23", "PA24", "PA25", "PA26", "PA27" };
-static const char * const refclk0_groups[] = { "PA28" };
+static const char * const eq5p_eyeq5_timer0_groups[] = { "PA0", "PA1" };
+static const char * const eq5p_eyeq5_timer1_groups[] = { "PA2", "PA3" };
+static const char * const eq5p_eyeq5_timer2_groups[] = { "PA4", "PA5" };
+static const char * const eq5p_eyeq5_timer5_groups[] = { "PA6", "PA7", "PA8", "PA9" };
+static const char * const eq5p_eyeq5_uart0_groups[] = { "PA10", "PA11" };
+static const char * const eq5p_eyeq5_uart1_groups[] = { "PA12", "PA13" };
+static const char * const eq5p_eyeq5_can0_groups[] = { "PA14", "PA15" };
+static const char * const eq5p_eyeq5_can1_groups[] = { "PA16", "PA17" };
+static const char * const eq5p_eyeq5_spi0_groups[] = { "PA18", "PA19", "PA20", "PA21", "PA22" };
+static const char * const eq5p_eyeq5_spi1_groups[] = { "PA23", "PA24", "PA25", "PA26", "PA27" };
+static const char * const eq5p_eyeq5_refclk0_groups[] = { "PA28" };
 
 /* Groups of functions on bank B */
-static const char * const timer3_groups[] = { "PB0", "PB1" };
-static const char * const timer4_groups[] = { "PB2", "PB3" };
-static const char * const timer6_groups[] = { "PB4", "PB5", "PB6", "PB7" };
-static const char * const uart2_groups[] = { "PB8", "PB9" };
-static const char * const can2_groups[] = { "PB10", "PB11" };
-static const char * const spi2_groups[] = { "PB12", "PB13", "PB14", "PB15", "PB16" };
-static const char * const spi3_groups[] = { "PB17", "PB18", "PB19", "PB20", "PB21" };
-static const char * const mclk0_groups[] = { "PB22" };
+static const char * const eq5p_eyeq5_timer3_groups[] = { "PB0", "PB1" };
+static const char * const eq5p_eyeq5_timer4_groups[] = { "PB2", "PB3" };
+static const char * const eq5p_eyeq5_timer6_groups[] = { "PB4", "PB5", "PB6", "PB7" };
+static const char * const eq5p_eyeq5_uart2_groups[] = { "PB8", "PB9" };
+static const char * const eq5p_eyeq5_can2_groups[] = { "PB10", "PB11" };
+static const char * const eq5p_eyeq5_spi2_groups[] = { "PB12", "PB13", "PB14", "PB15", "PB16" };
+static const char * const eq5p_eyeq5_spi3_groups[] = { "PB17", "PB18", "PB19", "PB20", "PB21" };
+static const char * const eq5p_eyeq5_mclk0_groups[] = { "PB22" };
 
-static const struct pinfunction eq5p_functions[] = {
-	/* GPIO having a fixed index is depended upon, see GPIO_FUNC_SELECTOR. */
-	PINCTRL_PINFUNCTION("gpio", gpio_groups, ARRAY_SIZE(gpio_groups)),
-#define GPIO_FUNC_SELECTOR 0
+static const struct pinfunction eq5p_eyeq5_functions[] = {
+	/* GPIO having a fixed index is depended upon, see EQ5P_GPIO_FUNC_SELECTOR. */
+	EQ5P_PINFUNCTION("gpio", eq5p_eyeq5_gpio_groups),
 
 	/* Bank A functions */
-	PINCTRL_PINFUNCTION("timer0", timer0_groups, ARRAY_SIZE(timer0_groups)),
-	PINCTRL_PINFUNCTION("timer1", timer1_groups, ARRAY_SIZE(timer1_groups)),
-	PINCTRL_PINFUNCTION("timer2", timer2_groups, ARRAY_SIZE(timer2_groups)),
-	PINCTRL_PINFUNCTION("timer5", timer5_groups, ARRAY_SIZE(timer5_groups)),
-	PINCTRL_PINFUNCTION("uart0", uart0_groups, ARRAY_SIZE(uart0_groups)),
-	PINCTRL_PINFUNCTION("uart1", uart1_groups, ARRAY_SIZE(uart1_groups)),
-	PINCTRL_PINFUNCTION("can0", can0_groups, ARRAY_SIZE(can0_groups)),
-	PINCTRL_PINFUNCTION("can1", can1_groups, ARRAY_SIZE(can1_groups)),
-	PINCTRL_PINFUNCTION("spi0", spi0_groups, ARRAY_SIZE(spi0_groups)),
-	PINCTRL_PINFUNCTION("spi1", spi1_groups, ARRAY_SIZE(spi1_groups)),
-	PINCTRL_PINFUNCTION("refclk0", refclk0_groups, ARRAY_SIZE(refclk0_groups)),
+	EQ5P_PINFUNCTION("timer0", eq5p_eyeq5_timer0_groups),
+	EQ5P_PINFUNCTION("timer1", eq5p_eyeq5_timer1_groups),
+	EQ5P_PINFUNCTION("timer2", eq5p_eyeq5_timer2_groups),
+	EQ5P_PINFUNCTION("timer5", eq5p_eyeq5_timer5_groups),
+	EQ5P_PINFUNCTION("uart0", eq5p_eyeq5_uart0_groups),
+	EQ5P_PINFUNCTION("uart1", eq5p_eyeq5_uart1_groups),
+	EQ5P_PINFUNCTION("can0", eq5p_eyeq5_can0_groups),
+	EQ5P_PINFUNCTION("can1", eq5p_eyeq5_can1_groups),
+	EQ5P_PINFUNCTION("spi0", eq5p_eyeq5_spi0_groups),
+	EQ5P_PINFUNCTION("spi1", eq5p_eyeq5_spi1_groups),
+	EQ5P_PINFUNCTION("refclk0", eq5p_eyeq5_refclk0_groups),
 
 	/* Bank B functions */
-	PINCTRL_PINFUNCTION("timer3", timer3_groups, ARRAY_SIZE(timer3_groups)),
-	PINCTRL_PINFUNCTION("timer4", timer4_groups, ARRAY_SIZE(timer4_groups)),
-	PINCTRL_PINFUNCTION("timer6", timer6_groups, ARRAY_SIZE(timer6_groups)),
-	PINCTRL_PINFUNCTION("uart2", uart2_groups, ARRAY_SIZE(uart2_groups)),
-	PINCTRL_PINFUNCTION("can2", can2_groups, ARRAY_SIZE(can2_groups)),
-	PINCTRL_PINFUNCTION("spi2", spi2_groups, ARRAY_SIZE(spi2_groups)),
-	PINCTRL_PINFUNCTION("spi3", spi3_groups, ARRAY_SIZE(spi3_groups)),
-	PINCTRL_PINFUNCTION("mclk0", mclk0_groups, ARRAY_SIZE(mclk0_groups)),
+	EQ5P_PINFUNCTION("timer3", eq5p_eyeq5_timer3_groups),
+	EQ5P_PINFUNCTION("timer4", eq5p_eyeq5_timer4_groups),
+	EQ5P_PINFUNCTION("timer6", eq5p_eyeq5_timer6_groups),
+	EQ5P_PINFUNCTION("uart2", eq5p_eyeq5_uart2_groups),
+	EQ5P_PINFUNCTION("can2", eq5p_eyeq5_can2_groups),
+	EQ5P_PINFUNCTION("spi2", eq5p_eyeq5_spi2_groups),
+	EQ5P_PINFUNCTION("spi3", eq5p_eyeq5_spi3_groups),
+	EQ5P_PINFUNCTION("mclk0", eq5p_eyeq5_mclk0_groups),
+};
+
+static const struct eq5p_bank eq5p_eyeq5_banks[] = {
+	{
+		.npins = EQ5P_EYEQ5_PIN_OFFSET_BANK_B,
+		.regs = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},
+	},
+	{
+		.npins = ARRAY_SIZE(eq5p_eyeq5_pins) - EQ5P_EYEQ5_PIN_OFFSET_BANK_B,
+		.regs = {0x0C8, 0x0CC, 0x0D8, 0x0DC, 0x0B4},
+	},
+};
+
+static const struct eq5p_match_data eq5p_eyeq5_data = {
+	.npins = ARRAY_SIZE(eq5p_eyeq5_pins),
+	.nfunctions = ARRAY_SIZE(eq5p_eyeq5_functions),
+	.nbanks = ARRAY_SIZE(eq5p_eyeq5_banks),
+	.pins = eq5p_eyeq5_pins,
+	.functions = eq5p_eyeq5_functions,
+	.banks = eq5p_eyeq5_banks,
 };
 
 static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl,
-			     enum eq5p_bank bank, enum eq5p_regs reg,
-			     u32 mask, u32 val)
+			     const struct eq5p_bank *bank,
+			     enum eq5p_regs reg, u32 mask, u32 val)
 {
-	void __iomem *ptr = pctrl->base + eq5p_regs[bank][reg];
+	void __iomem *ptr = pctrl->base + bank->regs[reg];
 
 	writel((readl(ptr) & ~mask) | (val & mask), ptr);
 }
 
 static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl,
-			  enum eq5p_bank bank, enum eq5p_regs reg, int offset)
+			  const struct eq5p_bank *bank,
+			  enum eq5p_regs reg, int offset)
 {
-	u32 val = readl(pctrl->base + eq5p_regs[bank][reg]);
+	u32 val = readl(pctrl->base + bank->regs[reg]);
 
 	if (WARN_ON(offset > 31))
 		return false;
@@ -218,25 +250,29 @@ static bool eq5p_test_bit(const struct eq5p_pinctrl *pctrl,
 	return (val & BIT(offset)) != 0;
 }
 
-static enum eq5p_bank eq5p_pin_to_bank(unsigned int pin)
+static int eq5p_pin_to_bank_offset(const struct eq5p_pinctrl *pctrl, unsigned int pin,
+				   const struct eq5p_bank **bank, unsigned int *offset)
 {
-	if (pin < EQ5P_PIN_OFFSET_BANK_B)
-		return EQ5P_BANK_A;
-	else
-		return EQ5P_BANK_B;
-}
+	for (unsigned int i = 0; i < pctrl->data->nbanks; i++) {
+		const struct eq5p_bank *_bank = &pctrl->data->banks[i];
+		unsigned int npins = _bank->npins;
 
-static unsigned int eq5p_pin_to_offset(unsigned int pin)
-{
-	if (pin < EQ5P_PIN_OFFSET_BANK_B)
-		return pin;
-	else
-		return pin - EQ5P_PIN_OFFSET_BANK_B;
+		if (pin < npins) {
+			*bank = _bank;
+			*offset = pin;
+			return 0;
+		}
+		pin -= npins;
+	}
+
+	return -EINVAL;
 }
 
 static int eq5p_pinctrl_get_groups_count(struct pinctrl_dev *pctldev)
 {
-	return ARRAY_SIZE(eq5p_pins);
+	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+	return pctrl->data->npins;
 }
 
 static const char *eq5p_pinctrl_get_group_name(struct pinctrl_dev *pctldev,
@@ -260,10 +296,15 @@ static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 {
 	enum pin_config_param param = pinconf_to_config_param(*config);
 	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
-	unsigned int offset = eq5p_pin_to_offset(pin);
-	enum eq5p_bank bank = eq5p_pin_to_bank(pin);
+	const struct eq5p_bank *bank;
+	unsigned int offset;
 	u32 val_ds, arg;
 	bool pd, pu;
+	int ret;
+
+	ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);
+	if (ret)
+		return ret;
 
 	pd = eq5p_test_bit(pctrl, bank, EQ5P_PD, offset);
 	pu = eq5p_test_bit(pctrl, bank, EQ5P_PU, offset);
@@ -281,10 +322,10 @@ static int eq5p_pinconf_get(struct pinctrl_dev *pctldev, unsigned int pin,
 	case PIN_CONFIG_DRIVE_STRENGTH:
 		offset *= 2; /* two bits per pin */
 		if (offset >= 32) {
-			val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_HIGH]);
+			val_ds = readl(pctrl->base + bank->regs[EQ5P_DS_HIGH]);
 			offset -= 32;
 		} else {
-			val_ds = readl(pctrl->base + eq5p_regs[bank][EQ5P_DS_LOW]);
+			val_ds = readl(pctrl->base + bank->regs[EQ5P_DS_LOW]);
 		}
 		arg = (val_ds >> offset) & EQ5P_DS_MASK;
 		break;
@@ -302,30 +343,35 @@ static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
 {
 	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 	const char *pin_name = pctrl->desc.pins[pin].name;
-	unsigned int offset = eq5p_pin_to_offset(pin);
-	enum eq5p_bank bank = eq5p_pin_to_bank(pin);
+	const struct eq5p_bank *bank;
 	const char *func_name, *bias;
 	unsigned long ds_config;
+	unsigned int offset;
 	u32 drive_strength;
 	bool pd, pu;
 	int i, j;
 
+	if (eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset)) {
+		seq_puts(s, "unknown pin");
+		return;
+	}
+
 	/*
 	 * First, let's get the function name. All pins have only two functions:
 	 * GPIO (IOCR == 0) and something else (IOCR == 1).
 	 */
 	if (eq5p_test_bit(pctrl, bank, EQ5P_IOCR, offset)) {
 		func_name = NULL;
-		for (i = 0; i < ARRAY_SIZE(eq5p_functions); i++) {
-			if (i == GPIO_FUNC_SELECTOR)
+		for (i = 0; i < pctrl->data->nfunctions; i++) {
+			if (i == EQ5P_GPIO_FUNC_SELECTOR)
 				continue;
 
-			for (j = 0; j < eq5p_functions[i].ngroups; j++) {
+			for (j = 0; j < pctrl->data->functions[i].ngroups; j++) {
 				/* Groups and pins are the same thing for us. */
-				const char *x = eq5p_functions[i].groups[j];
+				const char *x = pctrl->data->functions[i].groups[j];
 
 				if (strcmp(x, pin_name) == 0) {
-					func_name = eq5p_functions[i].name;
+					func_name = pctrl->data->functions[i].name;
 					break;
 				}
 			}
@@ -341,7 +387,7 @@ static void eq5p_pinctrl_pin_dbg_show(struct pinctrl_dev *pctldev,
 		if (!func_name)
 			func_name = "unknown";
 	} else {
-		func_name = eq5p_functions[GPIO_FUNC_SELECTOR].name;
+		func_name = pctrl->data->functions[EQ5P_GPIO_FUNC_SELECTOR].name;
 	}
 
 	/* Second, we retrieve the bias. */
@@ -376,13 +422,17 @@ static const struct pinctrl_ops eq5p_pinctrl_ops = {
 
 static int eq5p_pinmux_get_functions_count(struct pinctrl_dev *pctldev)
 {
-	return ARRAY_SIZE(eq5p_functions);
+	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+	return pctrl->data->nfunctions;
 }
 
 static const char *eq5p_pinmux_get_function_name(struct pinctrl_dev *pctldev,
 						 unsigned int selector)
 {
-	return eq5p_functions[selector].name;
+	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+	return pctrl->data->functions[selector].name;
 }
 
 static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
@@ -390,8 +440,10 @@ static int eq5p_pinmux_get_function_groups(struct pinctrl_dev *pctldev,
 					   const char * const **groups,
 					   unsigned int *num_groups)
 {
-	*groups = eq5p_functions[selector].groups;
-	*num_groups = eq5p_functions[selector].ngroups;
+	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
+
+	*groups = pctrl->data->functions[selector].groups;
+	*num_groups = pctrl->data->functions[selector].ngroups;
 	return 0;
 }
 
@@ -399,12 +451,17 @@ static int eq5p_pinmux_set_mux(struct pinctrl_dev *pctldev,
 			       unsigned int func_selector, unsigned int pin)
 {
 	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
-	const char *func_name = eq5p_functions[func_selector].name;
+	const char *func_name = pctrl->data->functions[func_selector].name;
 	const char *group_name = pctldev->desc->pins[pin].name;
-	bool is_gpio = func_selector == GPIO_FUNC_SELECTOR;
-	unsigned int offset = eq5p_pin_to_offset(pin);
-	enum eq5p_bank bank = eq5p_pin_to_bank(pin);
+	bool is_gpio = func_selector == EQ5P_GPIO_FUNC_SELECTOR;
+	const struct eq5p_bank *bank;
+	unsigned int offset;
 	u32 mask, val;
+	int ret;
+
+	ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);
+	if (ret)
+		return ret;
 
 	dev_dbg(pctldev->dev, "func=%s group=%s\n", func_name, group_name);
 
@@ -419,7 +476,7 @@ static int eq5p_pinmux_gpio_request_enable(struct pinctrl_dev *pctldev,
 					   unsigned int pin)
 {
 	/* Pin numbers and group selectors are the same thing in our case. */
-	return eq5p_pinmux_set_mux(pctldev, GPIO_FUNC_SELECTOR, pin);
+	return eq5p_pinmux_set_mux(pctldev, EQ5P_GPIO_FUNC_SELECTOR, pin);
 }
 
 static const struct pinmux_ops eq5p_pinmux_ops = {
@@ -435,10 +492,15 @@ static int eq5p_pinconf_set_drive_strength(struct pinctrl_dev *pctldev,
 					   unsigned int pin, u32 arg)
 {
 	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
-	unsigned int offset = eq5p_pin_to_offset(pin);
-	enum eq5p_bank bank = eq5p_pin_to_bank(pin);
+	const struct eq5p_bank *bank;
+	unsigned int offset;
 	unsigned int reg;
 	u32 mask, val;
+	int ret;
+
+	ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);
+	if (ret)
+		return ret;
 
 	if (arg & ~EQ5P_DS_MASK) {
 		dev_err(pctldev->dev, "Unsupported drive strength: %u\n", arg);
@@ -465,11 +527,16 @@ static int eq5p_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
 {
 	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
 	const char *pin_name = pctldev->desc->pins[pin].name;
-	unsigned int offset = eq5p_pin_to_offset(pin);
-	enum eq5p_bank bank = eq5p_pin_to_bank(pin);
 	struct device *dev = pctldev->dev;
+	const struct eq5p_bank *bank;
+	unsigned int offset;
 	u32 val = BIT(offset);
 	unsigned int i;
+	int ret;
+
+	ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);
+	if (ret)
+		return ret;
 
 	for (i = 0; i < num_configs; i++) {
 		enum pin_config_param param = pinconf_to_config_param(configs[i]);
@@ -530,22 +597,57 @@ static const struct pinconf_ops eq5p_pinconf_ops = {
 	.pin_config_group_set = eq5p_pinconf_set,
 };
 
+static void eq5p_of_node_put(void *_dev)
+{
+	struct device *dev = _dev;
+
+	of_node_put(dev->of_node);
+}
+
 static int eq5p_probe(struct auxiliary_device *adev,
 		      const struct auxiliary_device_id *id)
 {
+	const struct of_device_id *match;
 	struct device *dev = &adev->dev;
 	struct pinctrl_dev *pctldev;
 	struct eq5p_pinctrl *pctrl;
+	bool need_of_put = false;
 	int ret;
 
+	/*
+	 * We are an auxiliary device of clk-eyeq. We do not have an OF node by
+	 * default; let's reuse our parent's OF node if not already set.
+	 */
+	if (!dev->of_node) {
+		device_set_of_node_from_dev(dev, dev->parent);
+		need_of_put = true;
+	}
+	if (!dev->of_node)
+		return -ENODEV;
+
+	if (need_of_put) {
+		ret = devm_add_action_or_reset(dev, eq5p_of_node_put, dev);
+		if (ret)
+			return ret;
+	}
+
+	/*
+	 * Using our newfound OF node, we can get match data. We cannot use
+	 * device_get_match_data() because it does not match reused OF nodes.
+	 */
+	match = of_match_node(dev->driver->of_match_table, dev->of_node);
+	if (!match || !match->data)
+		return -ENODEV;
+
 	pctrl = devm_kzalloc(dev, sizeof(*pctrl), GFP_KERNEL);
 	if (!pctrl)
 		return -ENOMEM;
 
 	pctrl->base = (void __iomem *)dev_get_platdata(dev);
+	pctrl->data = match->data;
 	pctrl->desc.name = dev_name(dev);
-	pctrl->desc.pins = eq5p_pins;
-	pctrl->desc.npins = ARRAY_SIZE(eq5p_pins);
+	pctrl->desc.pins = pctrl->data->pins;
+	pctrl->desc.npins = pctrl->data->npins;
 	pctrl->desc.pctlops = &eq5p_pinctrl_ops;
 	pctrl->desc.pmxops = &eq5p_pinmux_ops;
 	pctrl->desc.confops = &eq5p_pinconf_ops;
@@ -562,6 +664,12 @@ static int eq5p_probe(struct auxiliary_device *adev,
 	return 0;
 }
 
+static const struct of_device_id eq5p_match_table[] = {
+	{ .compatible = "mobileye,eyeq5-olb", .data = &eq5p_eyeq5_data },
+	{}
+};
+MODULE_DEVICE_TABLE(of, eq5p_match_table);
+
 static const struct auxiliary_device_id eq5p_id_table[] = {
 	{ .name = "clk_eyeq.pinctrl" },
 	{}
@@ -571,5 +679,8 @@ MODULE_DEVICE_TABLE(auxiliary, eq5p_id_table);
 static struct auxiliary_driver eq5p_driver = {
 	.probe = eq5p_probe,
 	.id_table = eq5p_id_table,
+	.driver = {
+		.of_match_table = eq5p_match_table,
+	}
 };
 module_auxiliary_driver(eq5p_driver);

-- 
2.52.0

Re: [PATCH 05/13] pinctrl: eyeq5: Use match data

[kernel test robot]

Hi Benoît,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 8f0b4cce4481fb22653697cced8d0d04027cb1e8]

url:    https://github.com/intel-lab-lkp/linux/commits/Beno-t-Monin/dt-bindings-mips-Add-Mobileye-EyeQ6Lplus-SoC/20251217-214926
base:   8f0b4cce4481fb22653697cced8d0d04027cb1e8
patch link:    https://lore.kernel.org/r/20251217-eyeq6lplus-v1-5-e9cdbd3af4c2%40bootlin.com
patch subject: [PATCH 05/13] pinctrl: eyeq5: Use match data
config: parisc-randconfig-r051-20251218 (https://download.01.org/0day-ci/archive/20251220/202512202102.TqCsNdqY-lkp@intel.com/config)
compiler: hppa-linux-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251220/202512202102.TqCsNdqY-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512202102.TqCsNdqY-lkp@intel.com/

All warnings (new ones prefixed by >>):

   In file included from include/linux/bits.h:5,
                    from include/linux/ratelimit_types.h:5,
                    from include/linux/ratelimit.h:5,
                    from include/linux/dev_printk.h:16,
                    from include/linux/device.h:15,
                    from include/linux/auxiliary_bus.h:11,
                    from drivers/pinctrl/pinctrl-eyeq5.c:21:
   drivers/pinctrl/pinctrl-eyeq5.c: In function 'eq5p_pinconf_set':
>> include/vdso/bits.h:7:40: warning: 'offset' is used uninitialized [-Wuninitialized]
       7 | #define BIT(nr)                 (UL(1) << (nr))
         |                                 ~~~~~~~^~~~~~~~
   drivers/pinctrl/pinctrl-eyeq5.c:533:19: note: in expansion of macro 'BIT'
     533 |         u32 val = BIT(offset);
         |                   ^~~
   drivers/pinctrl/pinctrl-eyeq5.c:532:22: note: 'offset' declared here
     532 |         unsigned int offset;
         |                      ^~~~~~


vim +/offset +7 include/vdso/bits.h

3945ff37d2f48d Vincenzo Frascino 2020-03-20  6  
3945ff37d2f48d Vincenzo Frascino 2020-03-20 @7  #define BIT(nr)			(UL(1) << (nr))
cbdb1f163af2bb Andy Shevchenko   2022-11-28  8  #define BIT_ULL(nr)		(ULL(1) << (nr))
3945ff37d2f48d Vincenzo Frascino 2020-03-20  9  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

Re: [PATCH 05/13] pinctrl: eyeq5: Use match data

[kernel test robot]

Hi Benoît,

kernel test robot noticed the following build warnings:

[auto build test WARNING on 8f0b4cce4481fb22653697cced8d0d04027cb1e8]

url:    https://github.com/intel-lab-lkp/linux/commits/Beno-t-Monin/dt-bindings-mips-Add-Mobileye-EyeQ6Lplus-SoC/20251217-214926
base:   8f0b4cce4481fb22653697cced8d0d04027cb1e8
patch link:    https://lore.kernel.org/r/20251217-eyeq6lplus-v1-5-e9cdbd3af4c2%40bootlin.com
patch subject: [PATCH 05/13] pinctrl: eyeq5: Use match data
config: parisc-allyesconfig (https://download.01.org/0day-ci/archive/20251220/202512202142.StvDXvbg-lkp@intel.com/config)
compiler: hppa-linux-gcc (GCC) 15.1.0
reproduce (this is a W=1 build): (https://download.01.org/0day-ci/archive/20251220/202512202142.StvDXvbg-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp@intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202512202142.StvDXvbg-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/pinctrl/pinctrl-eyeq5.c: In function 'eq5p_pinconf_set':
>> drivers/pinctrl/pinctrl-eyeq5.c:533:13: warning: 'offset' is used uninitialized [-Wuninitialized]
     533 |         u32 val = BIT(offset);
         |             ^~~
   drivers/pinctrl/pinctrl-eyeq5.c:532:22: note: 'offset' was declared here
     532 |         unsigned int offset;
         |                      ^~~~~~


vim +/offset +533 drivers/pinctrl/pinctrl-eyeq5.c

41795aa1f56a6e Théo Lebrun  2024-07-30  524  
41795aa1f56a6e Théo Lebrun  2024-07-30  525  static int eq5p_pinconf_set(struct pinctrl_dev *pctldev, unsigned int pin,
41795aa1f56a6e Théo Lebrun  2024-07-30  526  			    unsigned long *configs, unsigned int num_configs)
41795aa1f56a6e Théo Lebrun  2024-07-30  527  {
41795aa1f56a6e Théo Lebrun  2024-07-30  528  	struct eq5p_pinctrl *pctrl = pinctrl_dev_get_drvdata(pctldev);
41795aa1f56a6e Théo Lebrun  2024-07-30  529  	const char *pin_name = pctldev->desc->pins[pin].name;
41795aa1f56a6e Théo Lebrun  2024-07-30  530  	struct device *dev = pctldev->dev;
e3ba56038b97ee Benoît Monin 2025-12-17  531  	const struct eq5p_bank *bank;
e3ba56038b97ee Benoît Monin 2025-12-17  532  	unsigned int offset;
41795aa1f56a6e Théo Lebrun  2024-07-30 @533  	u32 val = BIT(offset);
41795aa1f56a6e Théo Lebrun  2024-07-30  534  	unsigned int i;
e3ba56038b97ee Benoît Monin 2025-12-17  535  	int ret;
e3ba56038b97ee Benoît Monin 2025-12-17  536  
e3ba56038b97ee Benoît Monin 2025-12-17  537  	ret = eq5p_pin_to_bank_offset(pctrl, pin, &bank, &offset);
e3ba56038b97ee Benoît Monin 2025-12-17  538  	if (ret)
e3ba56038b97ee Benoît Monin 2025-12-17  539  		return ret;
41795aa1f56a6e Théo Lebrun  2024-07-30  540  
41795aa1f56a6e Théo Lebrun  2024-07-30  541  	for (i = 0; i < num_configs; i++) {
41795aa1f56a6e Théo Lebrun  2024-07-30  542  		enum pin_config_param param = pinconf_to_config_param(configs[i]);
41795aa1f56a6e Théo Lebrun  2024-07-30  543  		u32 arg = pinconf_to_config_argument(configs[i]);
41795aa1f56a6e Théo Lebrun  2024-07-30  544  
41795aa1f56a6e Théo Lebrun  2024-07-30  545  		switch (param) {
41795aa1f56a6e Théo Lebrun  2024-07-30  546  		case PIN_CONFIG_BIAS_DISABLE:
41795aa1f56a6e Théo Lebrun  2024-07-30  547  			dev_dbg(dev, "pin=%s bias_disable\n", pin_name);
41795aa1f56a6e Théo Lebrun  2024-07-30  548  
41795aa1f56a6e Théo Lebrun  2024-07-30  549  			eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0);
41795aa1f56a6e Théo Lebrun  2024-07-30  550  			eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0);
41795aa1f56a6e Théo Lebrun  2024-07-30  551  			break;
41795aa1f56a6e Théo Lebrun  2024-07-30  552  
41795aa1f56a6e Théo Lebrun  2024-07-30  553  		case PIN_CONFIG_BIAS_PULL_DOWN:
41795aa1f56a6e Théo Lebrun  2024-07-30  554  			dev_dbg(dev, "pin=%s bias_pull_down arg=%u\n",
41795aa1f56a6e Théo Lebrun  2024-07-30  555  				pin_name, arg);
41795aa1f56a6e Théo Lebrun  2024-07-30  556  
41795aa1f56a6e Théo Lebrun  2024-07-30  557  			if (arg == 0) /* cannot connect to GND */
41795aa1f56a6e Théo Lebrun  2024-07-30  558  				return -ENOTSUPP;
41795aa1f56a6e Théo Lebrun  2024-07-30  559  
41795aa1f56a6e Théo Lebrun  2024-07-30  560  			eq5p_update_bits(pctrl, bank, EQ5P_PD, val, val);
41795aa1f56a6e Théo Lebrun  2024-07-30  561  			eq5p_update_bits(pctrl, bank, EQ5P_PU, val, 0);
41795aa1f56a6e Théo Lebrun  2024-07-30  562  			break;
41795aa1f56a6e Théo Lebrun  2024-07-30  563  
41795aa1f56a6e Théo Lebrun  2024-07-30  564  		case PIN_CONFIG_BIAS_PULL_UP:
41795aa1f56a6e Théo Lebrun  2024-07-30  565  			dev_dbg(dev, "pin=%s bias_pull_up arg=%u\n",
41795aa1f56a6e Théo Lebrun  2024-07-30  566  				pin_name, arg);
41795aa1f56a6e Théo Lebrun  2024-07-30  567  
41795aa1f56a6e Théo Lebrun  2024-07-30  568  			if (arg == 0) /* cannot connect to VDD */
41795aa1f56a6e Théo Lebrun  2024-07-30  569  				return -ENOTSUPP;
41795aa1f56a6e Théo Lebrun  2024-07-30  570  
41795aa1f56a6e Théo Lebrun  2024-07-30  571  			eq5p_update_bits(pctrl, bank, EQ5P_PD, val, 0);
41795aa1f56a6e Théo Lebrun  2024-07-30  572  			eq5p_update_bits(pctrl, bank, EQ5P_PU, val, val);
41795aa1f56a6e Théo Lebrun  2024-07-30  573  			break;
41795aa1f56a6e Théo Lebrun  2024-07-30  574  
41795aa1f56a6e Théo Lebrun  2024-07-30  575  		case PIN_CONFIG_DRIVE_STRENGTH:
41795aa1f56a6e Théo Lebrun  2024-07-30  576  			dev_dbg(dev, "pin=%s drive_strength arg=%u\n",
41795aa1f56a6e Théo Lebrun  2024-07-30  577  				pin_name, arg);
41795aa1f56a6e Théo Lebrun  2024-07-30  578  
41795aa1f56a6e Théo Lebrun  2024-07-30  579  			eq5p_pinconf_set_drive_strength(pctldev, pin, arg);
41795aa1f56a6e Théo Lebrun  2024-07-30  580  			break;
41795aa1f56a6e Théo Lebrun  2024-07-30  581  
41795aa1f56a6e Théo Lebrun  2024-07-30  582  		default:
41795aa1f56a6e Théo Lebrun  2024-07-30  583  			dev_err(dev, "Unsupported pinconf %u\n", param);
41795aa1f56a6e Théo Lebrun  2024-07-30  584  			return -ENOTSUPP;
41795aa1f56a6e Théo Lebrun  2024-07-30  585  		}
41795aa1f56a6e Théo Lebrun  2024-07-30  586  	}
41795aa1f56a6e Théo Lebrun  2024-07-30  587  
41795aa1f56a6e Théo Lebrun  2024-07-30  588  	return 0;
41795aa1f56a6e Théo Lebrun  2024-07-30  589  }
41795aa1f56a6e Théo Lebrun  2024-07-30  590  

-- 
0-DAY CI Kernel Test Service
https://github.com/intel/lkp-tests/wiki

[PATCH 06/13] pinctrl: eyeq5: Add Mobileye EyeQ6Lplus OLB

[Benoît Monin]

Add the match data for the pinctrl found in the EyeQ6Lplus OLB. The pin
control is identical in function to the one present in the EyeQ5 but
has a single bank of 32 pins.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/pinctrl/Kconfig         |  4 +-
 drivers/pinctrl/pinctrl-eyeq5.c | 95 +++++++++++++++++++++++++++++++++++++++++
 2 files changed, 97 insertions(+), 2 deletions(-)

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig
index bc7f37afc48b..c81568d835e6 100644
--- a/drivers/pinctrl/Kconfig
+++ b/drivers/pinctrl/Kconfig
@@ -248,11 +248,11 @@ config PINCTRL_EQUILIBRIUM
 config PINCTRL_EYEQ5
 	bool "Mobileye EyeQ5 pinctrl driver"
 	depends on OF
-	depends on MACH_EYEQ5 || COMPILE_TEST
+	depends on MACH_EYEQ5 || MACH_EYEQ6LPLUS || COMPILE_TEST
 	select PINMUX
 	select GENERIC_PINCONF
 	select AUXILIARY_BUS
-	default MACH_EYEQ5
+	default MACH_EYEQ5 || MACH_EYEQ6LPLUS
 	help
 	  Pin controller driver for the Mobileye EyeQ5 platform. It does both
 	  pin config & pin muxing. It does not handle GPIO.
diff --git a/drivers/pinctrl/pinctrl-eyeq5.c b/drivers/pinctrl/pinctrl-eyeq5.c
index e48add1d965d..729fdf7cbbc2 100644
--- a/drivers/pinctrl/pinctrl-eyeq5.c
+++ b/drivers/pinctrl/pinctrl-eyeq5.c
@@ -229,6 +229,100 @@ static const struct eq5p_match_data eq5p_eyeq5_data = {
 	.banks = eq5p_eyeq5_banks,
 };
 
+static const struct pinctrl_pin_desc eq5p_eyeq6lplus_pins[] = {
+	PINCTRL_PIN(0,  "PA0"),  /* GPIO_A0_TIMER0_CK0 */
+	PINCTRL_PIN(1,  "PA1"),  /* GPIO_A1_TIMER0_EOC */
+	PINCTRL_PIN(2,  "PA2"),  /* GPIO_A2_TIMER1_CK */
+	PINCTRL_PIN(3,  "PA3"),  /* GPIO_A3_TIMER1_EOC1 */
+	PINCTRL_PIN(4,  "PA4"),  /* GPIO_A4_SSI_UART_RX */
+	PINCTRL_PIN(5,  "PA5"),  /* GPIO_A5_SSI_UART_TX */
+	PINCTRL_PIN(6,  "PA6"),  /* GPIO_A6_SPI_0_CS */
+	PINCTRL_PIN(7,  "PA7"),  /* GPIO_A7_SPI_0_DI */
+	PINCTRL_PIN(8,  "PA8"),  /* GPIO_A8_SPI_0_CK */
+	PINCTRL_PIN(9,  "PA9"),  /* GPIO_A9_SPI_0_DO */
+	PINCTRL_PIN(10, "PA10"), /* GPIO_A10_SPI_0_CS1 */
+	PINCTRL_PIN(11, "PA11"), /* GPIO_A11_UART_0_RX */
+	PINCTRL_PIN(12, "PA12"), /* GPIO_A12_UART_0_TX */
+	PINCTRL_PIN(13, "PA13"), /* GPIO_A13_TIMER2_CK */
+	PINCTRL_PIN(14, "PA14"), /* GPIO_A14_TIMER2_EOC */
+	PINCTRL_PIN(15, "PA15"), /* GPIO_A15_TIMER3_CK */
+	PINCTRL_PIN(16, "PA16"), /* GPIO_A16_TIMER_EOC */
+	PINCTRL_PIN(17, "PA17"), /* GPIO_A17_TIMER_EXT0_INCA P1 */
+	PINCTRL_PIN(18, "PA18"), /* GPIO_A18_TIMER_EXT0_INCA P2 */
+	PINCTRL_PIN(19, "PA19"), /* GPIO_A19_TIMER_EXT0_OUT CMP1 */
+	PINCTRL_PIN(20, "PA20"), /* GPIO_A20_TIMER_EXT0_OUT CMP2 */
+	PINCTRL_PIN(21, "PA21"), /* GPIO_A21_SPI_1_CS0 */
+	PINCTRL_PIN(22, "PA22"), /* GPIO_A22_SPI_1_DI */
+	PINCTRL_PIN(23, "PA23"), /* GPIO_A23_SPI_1_CK */
+	PINCTRL_PIN(24, "PA24"), /* GPIO_A24_SPI_1_DO */
+	PINCTRL_PIN(25, "PA25"), /* GPIO_A25_SPI_1_CS1 */
+	PINCTRL_PIN(26, "PA26"), /* GPIO_A26_TIMER_EXT1_INCA P1 */
+	PINCTRL_PIN(27, "PA27"), /* GPIO_A27_TIMER_EXT1_INCA P2 */
+	PINCTRL_PIN(28, "PA28"), /* GPIO_A28_TIMER_EXT1_OUTC MP1 */
+	PINCTRL_PIN(29, "PA29"), /* GPIO_A29_TIMER_EXT1_OUTC MP2 */
+	PINCTRL_PIN(30, "PA30"), /* GPIO_A30_EXT_CLK */
+	PINCTRL_PIN(31, "PA31"), /* GPIO_A31_VDI_MCLK */
+};
+
+static const char * const eq5p_eyeq6lplus_gpio_groups[] = {
+	/* Bank A */
+	"PA0",  "PA1",  "PA2",  "PA3",  "PA4",  "PA5",  "PA6",  "PA7",
+	"PA8",  "PA9",  "PA10", "PA11", "PA12", "PA13", "PA14", "PA15",
+	"PA16", "PA17", "PA18", "PA19", "PA20", "PA21", "PA22", "PA23",
+	"PA24", "PA25", "PA26", "PA27", "PA28", "PA29", "PA30", "PA31",
+};
+
+/* Groups of functions on bank A */
+static const char * const eq5p_eyeq6lplus_timer0_groups[] = { "PA0", "PA1" };
+static const char * const eq5p_eyeq6lplus_timer1_groups[] = { "PA2", "PA3" };
+static const char * const eq5p_eyeq6lplus_uart_ssi_groups[] = { "PA4", "PA5" };
+static const char * const eq5p_eyeq6lplus_spi0_groups[] = { "PA6", "PA7", "PA8", "PA9", "PA10" };
+static const char * const eq5p_eyeq6lplus_uart0_groups[] = { "PA11", "PA12" };
+static const char * const eq5p_eyeq6lplus_timer2_groups[] = { "PA13", "PA14" };
+static const char * const eq5p_eyeq6lplus_timer3_groups[] = { "PA15", "PA16" };
+static const char * const eq5p_eyeq6lplus_timer_ext0_groups[] = { "PA17", "PA18", "PA19", "PA20" };
+static const char * const eq5p_eyeq6lplus_spi1_groups[] = {
+	"PA21", "PA22", "PA23", "PA24", "PA25"
+};
+static const char * const eq5p_eyeq6lplus_timer_ext1_groups[] = { "PA26", "PA27", "PA28", "PA29" };
+static const char * const eq5p_eyeq6lplus_ext_ref_clk_groups[] = { "PA30" };
+static const char * const eq5p_eyeq6lplus_mipi_ref_clk_groups[] = { "PA31" };
+
+static const struct pinfunction eq5p_eyeq6lplus_functions[] = {
+	/* gpios function */
+	EQ5P_PINFUNCTION("gpio", eq5p_eyeq6lplus_gpio_groups),
+
+	/* Bank A alternate functions */
+	EQ5P_PINFUNCTION("timer0", eq5p_eyeq6lplus_timer0_groups),
+	EQ5P_PINFUNCTION("timer1", eq5p_eyeq6lplus_timer1_groups),
+	EQ5P_PINFUNCTION("uart_ssi", eq5p_eyeq6lplus_uart_ssi_groups),
+	EQ5P_PINFUNCTION("spi0", eq5p_eyeq6lplus_spi0_groups),
+	EQ5P_PINFUNCTION("uart0", eq5p_eyeq6lplus_uart0_groups),
+	EQ5P_PINFUNCTION("timer2", eq5p_eyeq6lplus_timer2_groups),
+	EQ5P_PINFUNCTION("timer3", eq5p_eyeq6lplus_timer3_groups),
+	EQ5P_PINFUNCTION("timer_ext0", eq5p_eyeq6lplus_timer_ext0_groups),
+	EQ5P_PINFUNCTION("spi1", eq5p_eyeq6lplus_spi1_groups),
+	EQ5P_PINFUNCTION("timer_ext1", eq5p_eyeq6lplus_timer_ext1_groups),
+	EQ5P_PINFUNCTION("ext_ref_clk", eq5p_eyeq6lplus_ext_ref_clk_groups),
+	EQ5P_PINFUNCTION("mipi_ref_clk", eq5p_eyeq6lplus_mipi_ref_clk_groups),
+};
+
+static const struct eq5p_bank eq5p_eyeq6lplus_banks[] = {
+	{
+		.npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins),
+		.regs = {0x0C0, 0x0C4, 0x0D0, 0x0D4, 0x0B0},
+	},
+};
+
+static const struct eq5p_match_data eq5p_eyeq6lplus_data = {
+	.npins = ARRAY_SIZE(eq5p_eyeq6lplus_pins),
+	.nfunctions = ARRAY_SIZE(eq5p_eyeq6lplus_functions),
+	.nbanks = ARRAY_SIZE(eq5p_eyeq6lplus_banks),
+	.pins = eq5p_eyeq6lplus_pins,
+	.functions = eq5p_eyeq6lplus_functions,
+	.banks = eq5p_eyeq6lplus_banks,
+};
+
 static void eq5p_update_bits(const struct eq5p_pinctrl *pctrl,
 			     const struct eq5p_bank *bank,
 			     enum eq5p_regs reg, u32 mask, u32 val)
@@ -666,6 +760,7 @@ static int eq5p_probe(struct auxiliary_device *adev,
 
 static const struct of_device_id eq5p_match_table[] = {
 	{ .compatible = "mobileye,eyeq5-olb", .data = &eq5p_eyeq5_data },
+	{ .compatible = "mobileye,eyeq6lplus-olb", .data = &eq5p_eyeq6lplus_data },
 	{}
 };
 MODULE_DEVICE_TABLE(of, eq5p_match_table);

-- 
2.52.0

[PATCH 07/13] clk: eyeq: Skip post-divisor when computing PLL frequency

[Benoît Monin]

The output of the PLL is routed before the post-divisor so it should be
ignored when computing the frequency of the PLL, functional change is
implemented to reflect how the clock signal is wired internally.

For the PLL of the EyeQ5, EyeQ6L, and EyeQ6H, this change has no impact
as the post-divisor is either reported as disabled or set to 1. The PLL
frequency is the same before and after the post-divisor.

For the PLL in EyeQ6Lplus, however, the post-divisor is not 1, so it must
be ignored to compute the correct frequency.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index ea1c3d78e7cd..182b408b6aa4 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -177,8 +177,6 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
 
 	*mult = FIELD_GET(PCSR0_INTIN, r0);
 	*div = FIELD_GET(PCSR0_REF_DIV, r0);
-	if (r0 & PCSR0_FOUTPOSTDIV_EN)
-		*div *= FIELD_GET(PCSR0_POST_DIV1, r0) * FIELD_GET(PCSR0_POST_DIV2, r0);
 
 	/* Fractional mode, in 2^20 (0x100000) parts. */
 	if (r0 & PCSR0_DSM_EN) {

-- 
2.52.0

[PATCH 08/13] clk: eyeq: Adjust PLL accuracy computation

[Benoît Monin]

The spread spectrum of the PLL found in eyeQ OLB is in 1/1024 parts of the
frequency, not in 1/1000, so adjust the computation of the accuracy. Also
correct the downspreading to match.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/clk-eyeq.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 182b408b6aa4..8fb32f365f3d 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -163,7 +163,7 @@ static void eqc_pll_downshift_factors(unsigned long *mult, unsigned long *div)
 static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
 				   unsigned long *div, unsigned long *acc)
 {
-	u32 spread;
+	unsigned long spread;
 
 	if (r0 & PCSR0_BYPASS) {
 		*mult = 1;
@@ -195,23 +195,23 @@ static int eqc_pll_parse_registers(u32 r0, u32 r1, unsigned long *mult,
 	/*
 	 * Spread spectrum.
 	 *
-	 * Spread is 1/1000 parts of frequency, accuracy is half of
-	 * that. To get accuracy, convert to ppb (parts per billion).
+	 * Spread is in 1/1024 parts of frequency. Clock accuracy
+	 * is half the spread value expressed in parts per billion.
 	 *
-	 * acc = spread * 1e6 / 2
-	 *   with acc in parts per billion and,
-	 *        spread in parts per thousand.
+	 * accuracy = (spread * 1e9) / (1024 * 2)
+	 *
+	 * Care is taken to avoid overflowing or losing precision.
 	 */
 	spread = FIELD_GET(PCSR1_SPREAD, r1);
-	*acc = spread * 500000;
+	*acc = DIV_ROUND_CLOSEST(spread * 1000000000, 1024 * 2);
 
 	if (r1 & PCSR1_DOWN_SPREAD) {
 		/*
 		 * Downspreading: the central frequency is half a
 		 * spread lower.
 		 */
-		*mult *= 2000 - spread;
-		*div *= 2000;
+		*mult *= 2048 - spread;
+		*div *= 2048;
 
 		/*
 		 * Previous operation might overflow 32 bits. If it

-- 
2.52.0

[PATCH 09/13] clk: eyeq: Add Mobileye EyeQ6Lplus OLB

[Benoît Monin]

Declare the PLLs and fixed factors found in the EyeQ6Lplus OLB as part
of the match data for the "mobileye,eyeq6lplus-olb" compatible.

The PLL and fixed factor of the CPU are registered in early init as they
are required during the boot by the GIC timer.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 drivers/clk/Kconfig    |  4 +--
 drivers/clk/clk-eyeq.c | 70 ++++++++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 72 insertions(+), 2 deletions(-)

diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index 3a1611008e48..418c8f526279 100644
--- a/drivers/clk/Kconfig
+++ b/drivers/clk/Kconfig
@@ -236,9 +236,9 @@ config COMMON_CLK_EP93XX
 
 config COMMON_CLK_EYEQ
 	bool "Clock driver for the Mobileye EyeQ platform"
-	depends on MACH_EYEQ5 || MACH_EYEQ6H || COMPILE_TEST
+	depends on MACH_EYEQ5 || MACH_EYEQ6H || MACH_EYEQ6LPLUS || COMPILE_TEST
 	select AUXILIARY_BUS
-	default MACH_EYEQ5 || MACH_EYEQ6H
+	default MACH_EYEQ5 || MACH_EYEQ6H || MACH_EYEQ6LPLUS
 	help
 	  This driver provides clocks found on Mobileye EyeQ5, EyeQ6L and Eye6H
 	  SoCs. Controllers live in shared register regions called OLB. Driver
diff --git a/drivers/clk/clk-eyeq.c b/drivers/clk/clk-eyeq.c
index 8fb32f365f3d..239ddcb59383 100644
--- a/drivers/clk/clk-eyeq.c
+++ b/drivers/clk/clk-eyeq.c
@@ -45,6 +45,7 @@
 #include <linux/types.h>
 
 #include <dt-bindings/clock/mobileye,eyeq5-clk.h>
+#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h>
 
 /* In frac mode, it enables fractional noise canceling DAC. Else, no function. */
 #define PCSR0_DAC_EN			BIT(0)
@@ -571,6 +572,68 @@ static const struct eqc_match_data eqc_eyeq6l_match_data = {
 	.reset_auxdev_name = "reset",
 };
 
+static const struct eqc_pll eqc_eyeq6lplus_early_plls[] = {
+	{ .index = EQ6LPC_PLL_CPU, .name = "pll-cpu", .reg64 = 0x058 },
+};
+
+static const struct eqc_pll eqc_eyeq6lplus_plls[] = {
+	{ .index = EQ6LPC_PLL_DDR, .name = "pll-ddr", .reg64 = 0x02C },
+	{ .index = EQ6LPC_PLL_ACC, .name = "pll-acc", .reg64 = 0x034 },
+	{ .index = EQ6LPC_PLL_PER, .name = "pll-per", .reg64 = 0x03C },
+	{ .index = EQ6LPC_PLL_VDI, .name = "pll-vdi", .reg64 = 0x044 },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq6lplus_early_fixed_factors[] = {
+	{ EQ6LPC_CPU_OCC,	"occ-cpu",	1, 1,	EQ6LPC_PLL_CPU },
+};
+
+static const struct eqc_fixed_factor eqc_eyeq6lplus_fixed_factors[] = {
+	{ EQ6LPC_DDR_OCC,	"occ-ddr",	1, 1,	EQ6LPC_PLL_DDR },
+
+	{ EQ6LPC_ACC_VDI,	"vdi-div",	1, 10,	EQ6LPC_PLL_ACC },
+	{ EQ6LPC_ACC_OCC,	"occ-acc",	1, 1,	EQ6LPC_PLL_ACC },
+	{ EQ6LPC_ACC_FCMU,	"fcmu-a-clk",	1, 10,	EQ6LPC_ACC_OCC },
+
+	{ EQ6LPC_PER_OCC,	"occ-per",	1, 1,	EQ6LPC_PLL_PER },
+	{ EQ6LPC_PER_I2C_SER,	"i2c-ser-clk",	1, 10,	EQ6LPC_PER_OCC },
+	{ EQ6LPC_PER_PCLK,	"pclk",		1, 4,	EQ6LPC_PER_OCC },
+	{ EQ6LPC_PER_TSU,	"tsu-clk",	1, 8,	EQ6LPC_PER_OCC },
+	{ EQ6LPC_PER_OSPI,	"ospi-ref-clk",	1, 10,	EQ6LPC_PER_OCC },
+	{ EQ6LPC_PER_GPIO,	"gpio-clk",	1, 4,	EQ6LPC_PER_OCC },
+	{ EQ6LPC_PER_TIMER,	"timer-clk",	1, 4,	EQ6LPC_PER_OCC },
+	{ EQ6LPC_PER_I2C,	"i2c-clk",	1, 4,	EQ6LPC_PER_OCC },
+	{ EQ6LPC_PER_UART,	"uart-clk",	1, 4,	EQ6LPC_PER_OCC },
+	{ EQ6LPC_PER_SPI,	"spi-clk",	1, 4,	EQ6LPC_PER_OCC },
+	{ EQ6LPC_PER_PERIPH,	"periph-clk",	1, 1,	EQ6LPC_PER_OCC },
+
+	{ EQ6LPC_VDI_OCC,	"occ-vdi",	1, 1,	EQ6LPC_PLL_VDI },
+};
+
+static const struct eqc_early_match_data eqc_eyeq6lplus_early_match_data __initconst = {
+	.early_pll_count        = ARRAY_SIZE(eqc_eyeq6lplus_early_plls),
+	.early_plls             = eqc_eyeq6lplus_early_plls,
+
+	.early_fixed_factor_count       = ARRAY_SIZE(eqc_eyeq6lplus_early_fixed_factors),
+	.early_fixed_factors            = eqc_eyeq6lplus_early_fixed_factors,
+
+	.late_clk_count         = ARRAY_SIZE(eqc_eyeq6lplus_plls) +
+	ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors),
+};
+
+static const struct eqc_match_data eqc_eyeq6lplus_match_data = {
+	.pll_count      = ARRAY_SIZE(eqc_eyeq6lplus_plls),
+	.plls           = eqc_eyeq6lplus_plls,
+
+	.fixed_factor_count     = ARRAY_SIZE(eqc_eyeq6lplus_fixed_factors),
+	.fixed_factors          = eqc_eyeq6lplus_fixed_factors,
+
+	.reset_auxdev_name = "reset",
+	.pinctrl_auxdev_name = "pinctrl",
+
+	.early_clk_count = ARRAY_SIZE(eqc_eyeq6lplus_early_plls) +
+	ARRAY_SIZE(eqc_eyeq6lplus_early_fixed_factors),
+};
+
 static const struct eqc_match_data eqc_eyeq6h_west_match_data = {
 	.reset_auxdev_name = "reset_west",
 };
@@ -672,6 +735,7 @@ static const struct eqc_match_data eqc_eyeq6h_acc_match_data = {
 static const struct of_device_id eqc_match_table[] = {
 	{ .compatible = "mobileye,eyeq5-olb", .data = &eqc_eyeq5_match_data },
 	{ .compatible = "mobileye,eyeq6l-olb", .data = &eqc_eyeq6l_match_data },
+	{ .compatible = "mobileye,eyeq6lplus-olb", .data = &eqc_eyeq6lplus_match_data },
 	{ .compatible = "mobileye,eyeq6h-west-olb", .data = &eqc_eyeq6h_west_match_data },
 	{ .compatible = "mobileye,eyeq6h-east-olb", .data = &eqc_eyeq6h_east_match_data },
 	{ .compatible = "mobileye,eyeq6h-south-olb", .data = &eqc_eyeq6h_south_match_data },
@@ -855,3 +919,9 @@ static void __init eqc_eyeq6h_west_early_init(struct device_node *np)
 }
 CLK_OF_DECLARE_DRIVER(eqc_eyeq6h_west, "mobileye,eyeq6h-west-olb",
 		      eqc_eyeq6h_west_early_init);
+
+static void __init eqc_eyeq6lplus_early_init(struct device_node *np)
+{
+	eqc_early_init(np, &eqc_eyeq6lplus_early_match_data);
+}
+CLK_OF_DECLARE_DRIVER(eqc_eyeq6lplus, "mobileye,eyeq6lplus-olb", eqc_eyeq6lplus_early_init);

-- 
2.52.0

[PATCH 10/13] MIPS: Add Mobileye EyeQ6Lplus SoC dtsi

[Benoît Monin]

Add the device tree include files for the EyeQ6Lplus system on chip
from Mobileye.

Those files provide the initial support of the SoC:
* The I6500 CPU and GIC interrupt controller.
* The OLB ("Other Logic Block") providing clocks, resets and pin controls.
* One UART.
* One GPIO controller.
* Two SPI controllers, one in host mode and one in target mode.
* One octoSPI flash controller.
* Two I2C controllers.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi |  84 +++++++++++
 arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi      | 169 +++++++++++++++++++++++
 2 files changed, 253 insertions(+)

diff --git a/arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi b/arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi
new file mode 100644
index 000000000000..5cb0660f46c6
--- /dev/null
+++ b/arch/mips/boot/dts/mobileye/eyeq6lplus-pins.dtsi
@@ -0,0 +1,84 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+
+&olb {
+	timer0_pins: timer0-pins {
+		function = "timer0";
+		pins = "PA0", "PA1";
+	};
+	timer1_pins: timer1-pins {
+		function = "timer1";
+		pins = "PA2", "PA3";
+	};
+	uart_ssi_pins: uart-ssi-pins {
+		function = "uart_ssi";
+		pins = "PA4", "PA5";
+	};
+	spi0_pins: spi0-pins {
+		function = "spi0";
+		pins = "PA6", "PA7", "PA8", "PA9";
+	};
+	uart0_pins: uart0-pins {
+		function = "uart0";
+		pins = "PA11", "PA12";
+	};
+	timer2_pins: timer2-pins {
+		function = "timer2";
+		pins = "PA13", "PA14";
+	};
+	timer3_pins: timer3-pins {
+		function = "timer3";
+		pins = "PA15", "PA16";
+	};
+	timer_ext0_pins: timer-ext0-pins {
+		function = "timer_ext0";
+		pins = "PA17", "PA18", "PA19", "PA20";
+	};
+	timer_ext0_input_a_pins: timer-ext0-input-a-pins {
+		function = "timer_ext0";
+		pins = "PA17";
+	};
+	pps0_pins: pps0-pins {
+		function = "timer_ext0";
+		pins = "PA17";
+	};
+	timer_ext0_input_b_pins: timer-ext0-input-b-pins {
+		function = "timer_ext0";
+		pins = "PA18";
+	};
+	timer_ext0_output_pins: timer-ext0-output-pins {
+		function = "timer_ext0";
+		pins = "PA19", "PA20";
+	};
+	spi1_pins: spi1-pins {
+		function = "spi1";
+		pins = "PA21", "PA22", "PA23", "PA24";
+	};
+	spi1_reduced_pins: spi1-reduced-pins {
+		function = "spi1";
+		pins = "PA21", "PA22", "PA23";
+	};
+	timer_ext1_pins: timer-ext1-pins {
+		function = "timer_ext1";
+		pins = "PA26", "PA27", "PA28", "PA29";
+	};
+	timer_ext1_input_a_pins: timer-ext1-input-a-pins {
+		function = "timer_ext1";
+		pins = "PA26";
+	};
+	timer_ext1_input_b_pins: timer-ext1-input-b-pins {
+		function = "timer_ext1";
+		pins = "PA27";
+	};
+	timer_ext1_output_pins: timer-ext1-output-pins {
+		function = "timer_ext1";
+		pins = "PA28", "PA29";
+	};
+	ext_ref_clk_pins: ext-ref-clk-pins {
+		function = "ext_ref_clk";
+		pins = "PA30";
+	};
+	mipi_ref_clk_pins: mipi-ref-clk-pins {
+		function = "mipi_ref_clk";
+		pins = "PA31";
+	};
+};
diff --git a/arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi b/arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi
new file mode 100644
index 000000000000..28131ea558f6
--- /dev/null
+++ b/arch/mips/boot/dts/mobileye/eyeq6lplus.dtsi
@@ -0,0 +1,169 @@
+// SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+/*
+ * Copyright 2025 Mobileye Vision Technologies Ltd.
+ */
+
+#include <dt-bindings/interrupt-controller/mips-gic.h>
+
+#include <dt-bindings/clock/mobileye,eyeq6lplus-clk.h>
+
+/ {
+	#address-cells = <2>;
+	#size-cells = <2>;
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		cpu@0 {
+			device_type = "cpu";
+			compatible = "img,i6500";
+			reg = <0>;
+			clocks = <&olb EQ6LPC_CPU_OCC>;
+		};
+	};
+
+	cpu_intc: interrupt-controller {
+		compatible = "mti,cpu-interrupt-controller";
+		interrupt-controller;
+		#address-cells = <0>;
+		#interrupt-cells = <1>;
+	};
+
+	coherency-manager {
+		compatible = "mobileye,eyeq6-cm";
+	};
+
+	xtal: clock-30000000 {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <30000000>;
+	};
+
+	soc: soc {
+		compatible = "simple-bus";
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		olb: system-controller@e8400000 {
+			compatible = "mobileye,eyeq6lplus-olb", "syscon";
+			reg = <0 0xe8400000 0x0 0x80000>;
+			#reset-cells = <2>;
+			#clock-cells = <1>;
+			clocks = <&xtal>;
+			clock-names = "ref";
+		};
+
+		ospi: spi@e8800000 {
+			compatible = "mobileye,eyeq5-ospi", "cdns,qspi-nor";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0 0xe8800000 0x0 0x100000>,
+			      <0 0xb0000000 0x0 0x30000000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SHARED 10 IRQ_TYPE_LEVEL_HIGH>;
+			cdns,fifo-width = <4>;
+			cdns,trigger-address = <0x00000000>;
+			clocks  = <&olb EQ6LPC_PER_OSPI>;
+			status = "disabled";
+		};
+
+		spi0: spi@eac0d000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0 0xeac0d000 0x0 0x1000>;
+			clocks = <&olb EQ6LPC_PER_SPI>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SHARED 11 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&olb 0 0>;
+			reset-names = "spi";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		spi1: spi@eac0e000 {
+			compatible = "snps,dw-apb-ssi";
+			reg = <0 0xeac0e000 0x0 0x1000>;
+			spi-slave;
+			clocks = <&olb EQ6LPC_PER_SPI>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SHARED 12 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&olb 0 1>;
+			reset-names = "spi";
+			#address-cells = <0>;
+			#size-cells = <0>;
+			status = "disabled";
+		};
+
+		uart0: serial@eac10000 {
+			compatible = "snps,dw-apb-uart";
+			reg-shift = <2>;
+			reg-io-width = <4>;
+			clocks = <&olb EQ6LPC_PER_UART>;
+			clock-frequency = <15625000>;
+			reg = <0 0xeac10000 0x0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SHARED 8 IRQ_TYPE_LEVEL_HIGH>;
+			resets = <&olb 0 2>;
+			status = "disabled";
+		};
+
+		i2c0: i2c@eac11000 {
+			compatible = "mobileye,eyeq6lplus-i2c", "snps,designware-i2c";
+			reg = <0 0xeac11000 0x0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SHARED 6 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <400000>;
+			clocks = <&olb EQ6LPC_PER_I2C_SER>;
+			resets = <&olb 0 3>;
+			i2c-sda-hold-time-ns = <50>;
+			status = "disabled";
+		};
+
+		i2c1: i2c@eac12000 {
+			compatible = "mobileye,eyeq6lplus-i2c", "snps,designware-i2c";
+			reg = <0 0xeac12000 0x0 0x1000>;
+			interrupt-parent = <&gic>;
+			interrupts = <GIC_SHARED 7 IRQ_TYPE_LEVEL_HIGH>;
+			clock-frequency = <400000>;
+			clocks = <&olb EQ6LPC_PER_I2C_SER>;
+			resets = <&olb 0 4>;
+			i2c-sda-hold-time-ns = <50>;
+			status = "disabled";
+		};
+
+		gpio: gpio@eac14000 {
+			compatible = "snps,dw-apb-gpio";
+			reg = <0x0 0xeac14000 0x0 0x1000>;
+			#address-cells = <1>;
+			#size-cells = <0>;
+			resets = <&olb 0 13>;
+			porta: gpio-port@0 {
+				compatible = "snps,dw-apb-gpio-port";
+				gpio-controller;
+				#gpio-cells = <2>;
+				snps,nr-gpios = <32>;
+				gpio-ranges = <&olb 0 0 32>;
+				reg = <0>;
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				interrupt-parent = <&gic>;
+				interrupts = <GIC_SHARED 13 IRQ_TYPE_LEVEL_HIGH>;
+			};
+		};
+
+		gic: interrupt-controller@f0920000 {
+			compatible = "mti,gic";
+			reg = <0x0 0xf0920000 0x0 0x20000>;
+			interrupt-controller;
+			#interrupt-cells = <3>;
+			interrupt-parent = <&cpu_intc>;
+			timer {
+				compatible = "mti,gic-timer";
+				interrupts = <GIC_LOCAL 1 IRQ_TYPE_NONE>;
+				clocks = <&olb EQ6LPC_CPU_OCC>;
+			};
+		};
+	};
+};
+
+#include "eyeq6lplus-pins.dtsi"

-- 
2.52.0

[PATCH 11/13] MIPS: Add Mobileye EyeQ6Lplus evaluation board dts

[Benoît Monin]

Add the device tree of the evaluation board of the EyeQ6Lplus SoC.

The board comes with 2GB of RAM, an SPI NAND connected to the octoSPI
controller, and the two SPI controllers are connected to each other via
an intermediate MCU for loopback testing. The UART of the SoC is used
as the serial console.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 arch/mips/boot/dts/mobileye/Makefile            |   1 +
 arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts | 112 ++++++++++++++++++++++++
 2 files changed, 113 insertions(+)

diff --git a/arch/mips/boot/dts/mobileye/Makefile b/arch/mips/boot/dts/mobileye/Makefile
index 7cc89968aaac..9305dd01f4c8 100644
--- a/arch/mips/boot/dts/mobileye/Makefile
+++ b/arch/mips/boot/dts/mobileye/Makefile
@@ -3,3 +3,4 @@
 
 dtb-$(CONFIG_MACH_EYEQ5)		+= eyeq5-epm5.dtb
 dtb-$(CONFIG_MACH_EYEQ6H)		+= eyeq6h-epm6.dtb
+dtb-$(CONFIG_MACH_EYEQ6LPLUS)		+= eyeq6lplus-epm6.dtb
diff --git a/arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts b/arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts
new file mode 100644
index 000000000000..e42d05a4d213
--- /dev/null
+++ b/arch/mips/boot/dts/mobileye/eyeq6lplus-epm6.dts
@@ -0,0 +1,112 @@
+// SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+/*
+ * Copyright 2025 Mobileye Vision Technologies Ltd.
+ */
+
+/dts-v1/;
+
+#include "eyeq6lplus.dtsi"
+
+/ {
+	compatible = "mobileye,eyeq6lplus-epm6", "mobileye,eyeq6lplus";
+	model = "Mobileye EyeQ6Lplus Evaluation board";
+
+	aliases {
+		serial0 = &uart0;
+	};
+
+	chosen {
+		stdout-path = "serial0:921600n8";
+	};
+
+	memory@0 {
+		device_type = "memory";
+		reg = <0x1 0x00000000 0x0 0x80000000>;
+	};
+
+	reserved-memory {
+		#address-cells = <2>;
+		#size-cells = <2>;
+		ranges;
+
+		/* These reserved memory regions are also defined in bootmanager
+		 * for configuring inbound translation for BARS, don't change
+		 * these without syncing with bootmanager
+		 */
+		mhm_reserved_0: the-mhm-reserved-0 {
+			reg = <0x1 0x00000000 0x0 0x0000800>;
+		};
+		bm_logs_reserved: bm-logs-reserved {
+			reg = <0x1 0x0000800 0x0 0x000f800>;
+		};
+		shmem0_reserved: shmem@804000000 {
+			reg = <0x1 0x04000000 0x0 0x1000000>;
+		};
+		shmem1_reserved: shmem@805000000 {
+			reg = <0x1 0x05000000 0x0 0x1000000>;
+		};
+		mini_coredump0_reserved: mini-coredump0@806200000 {
+			reg = <0x1 0x06200000 0x0 0x100000>;
+		};
+		mailbox_reserved: mailbox-reserved {
+			reg = <0x1 0x06300000 0x0 0x000300>;
+		};
+		sys_logs_reserved: sys-logs-reserved {
+			reg = <0x1 0x10000000 0x0 0x800000>;
+		};
+		csl_policy_logs_reserved: csl-policy-logs-reserved {
+			reg = <0x1 0x10800000 0x0 0x10000>;
+		};
+	};
+};
+
+&ospi {
+	status = "okay";
+	flash@0 {
+		compatible = "spi-nand";
+		reg = <0>;
+		spi-max-frequency = <40000000>;
+		cdns,read-delay = <0>;
+		cdns,tshsl-ns = <400>;
+		cdns,tsd2d-ns = <120>;
+		cdns,tchsh-ns = <40>;
+		cdns,tslch-ns = <20>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <8>;
+	};
+};
+
+&spi0 {
+	pinctrl-0 = <&spi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	spidev@0 {
+		compatible = "lwn,bk4-spi";
+		spi-max-frequency = <5000000>;
+		reg = <0>;
+	};
+};
+
+&spi1 {
+	pinctrl-0 = <&spi1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+	slave {
+		compatible = "lwn,bk4-spi";
+		spi-max-frequency = <5000000>;
+	};
+};
+
+&uart0 {
+	pinctrl-0 = <&uart0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
+&i2c0 {
+	status = "okay";
+};
+
+&i2c1 {
+	status = "okay";
+};

-- 
2.52.0

Re: [PATCH 11/13] MIPS: Add Mobileye EyeQ6Lplus evaluation board dts

[Krzysztof Kozlowski]

On 17/12/2025 14:36, Benoît Monin wrote:
> +
> +&spi0 {
> +	pinctrl-0 = <&spi0_pins>;
> +	pinctrl-names = "default";
> +	status = "okay";
> +	spidev@0 {
> +		compatible = "lwn,bk4-spi";

NAK, you are not operating an excavator here.

Don't invent hardware.


Best regards,
Krzysztof

Re: [PATCH 11/13] MIPS: Add Mobileye EyeQ6Lplus evaluation board dts

[Benoît Monin]

Hi Krzysztof,

On 12/18/25 16:30, Krzysztof Kozlowski wrote:
> On 17/12/2025 14:36, Benoît Monin wrote:
>> +
>> +&spi0 {
>> +	pinctrl-0 = <&spi0_pins>;
>> +	pinctrl-names = "default";
>> +	status = "okay";
>> +	spidev@0 {
>> +		compatible = "lwn,bk4-spi";
> 
> NAK, you are not operating an excavator here.
> 
Indeed, I do not (and I should have known better...).

> Don't invent hardware.
> 
In my particular case of a microcontroller acting as an SPI "relay" on the
evaluation board, what would be the best way to describe it? It connects
the two SPI controllers of the SoC, one is a host and one is a target, so
it behave as an SPI target on one side and as an SPI host on the other.

The trivial devices bindings seems to be dedicated to devices, thus not for
SPI hosts. Do I need a dedicated binding or did I miss something I could
use for a trivial spidev slave?

> 
> Best regards,
> Krzysztof

Best regards,
-- 
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

Re: [PATCH 11/13] MIPS: Add Mobileye EyeQ6Lplus evaluation board dts

[Krzysztof Kozlowski]

On 19/12/2025 16:57, Benoît Monin wrote:
> Hi Krzysztof,
> 
> On 12/18/25 16:30, Krzysztof Kozlowski wrote:
>> On 17/12/2025 14:36, Benoît Monin wrote:
>>> +
>>> +&spi0 {
>>> +	pinctrl-0 = <&spi0_pins>;
>>> +	pinctrl-names = "default";
>>> +	status = "okay";
>>> +	spidev@0 {
>>> +		compatible = "lwn,bk4-spi";
>>
>> NAK, you are not operating an excavator here.
>>
> Indeed, I do not (and I should have known better...).
> 
>> Don't invent hardware.
>>
> In my particular case of a microcontroller acting as an SPI "relay" on the
> evaluation board, what would be the best way to describe it? It connects
> the two SPI controllers of the SoC, one is a host and one is a target, so
> it behave as an SPI target on one side and as an SPI host on the other.
> 
> The trivial devices bindings seems to be dedicated to devices, thus not for
> SPI hosts. Do I need a dedicated binding or did I miss something I could
> use for a trivial spidev slave?

In DT you describe only a real device connected here, so in case of your
evalboard - nothing can be described, because there is no such real device.

Best regards,
Krzysztof

Re: [PATCH 11/13] MIPS: Add Mobileye EyeQ6Lplus evaluation board dts

[Linus Walleij]

On Fri, Dec 19, 2025 at 4:57 PM Benoît Monin <benoit.monin@bootlin.com> wrote:

> In my particular case of a microcontroller acting as an SPI "relay" on the
> evaluation board, what would be the best way to describe it? It connects
> the two SPI controllers of the SoC, one is a host and one is a target, so
> it behave as an SPI target on one side and as an SPI host on the other.
>
> The trivial devices bindings seems to be dedicated to devices, thus not for
> SPI hosts. Do I need a dedicated binding or did I miss something I could
> use for a trivial spidev slave?

That needs to be detailed and discussed with the SPI maintainer on the SPI
devel list. (Added.)

Can you illustrate with a picture or so what is going on here?

Yours,
Linus Walleij

Re: [PATCH 11/13] MIPS: Add Mobileye EyeQ6Lplus evaluation board dts

[Benoît Monin]

Hi Linus,

On Thursday, 1 January 2026 at 23:42:36 CET, Linus Walleij wrote:
> On Fri, Dec 19, 2025 at 4:57 PM Benoît Monin <benoit.monin@bootlin.com> wrote:
> 
> > In my particular case of a microcontroller acting as an SPI "relay" on the
> > evaluation board, what would be the best way to describe it? It connects
> > the two SPI controllers of the SoC, one is a host and one is a target, so
> > it behave as an SPI target on one side and as an SPI host on the other.
> >
> > The trivial devices bindings seems to be dedicated to devices, thus not for
> > SPI hosts. Do I need a dedicated binding or did I miss something I could
> > use for a trivial spidev slave?
> 
> That needs to be detailed and discussed with the SPI maintainer on the SPI
> devel list. (Added.)
> 
> Can you illustrate with a picture or so what is going on here?
> 
> Yours,
> Linus Walleij
> 
Here is what it looks like on the evaluation board of the EyeQ6Lplus:

    +------------------------+          +------------------------+
    | EyeQ6Lplus SoC         |          | Evaluation board MCU   |
    |                        |          |                        |
    |           +------------+          +------------+           |
    |           | SPI host   |          | SPI target |           |
    |           |            |          |            |           |
    |           |        CLK >----------> CLK        |           |
    |           |        SDO >----------> SDI        |           |
    |           |        SDI <----------< SDO        |·····      |
    |           |        CS0 >----------> CS         |    ·      |
    |           +------------+          +------------+    ·      |
    |                        |          |                 · (1)  |
    |           +------------+          +------------+    ·      |
    |           | SPI target |          | SPI host   |    ·      |
    |           |            |          |            |<····      |
    |           |        CLK <----------< CLK        |           |
    |           |        SDI <----------< SDO        |           |
    |           |        SDO >----------> SDI        |           |
    |           |        CS  <----------< CS0        |           |
    |           +------------+          +------------+           |
    |                        |          |                        |
    +------------------------+          +------------------------+

(1): The MCU, when the chip select is asserted on its SPI target, starts
     a transaction on its SPI host side. It then copies data received by
     the target side to the host side.

With the spidev entries in the device tree, it is used to test that SPI
of the SoC is working with `spidev_test`. So the MCU is part of the test
harness found on the evaluation board.

If the SPI signals of the SoC had been routed to a header, we could do the
same test with jumper wires, directly connecting the host and the target.

Best regards,
-- 
Benoît Monin, Bootlin
Embedded Linux and Kernel engineering
https://bootlin.com

[PATCH 12/13] MIPS: config: add eyeq6lplus_defconfig

[Benoît Monin]

Add a default configuration for Mobileye EyeQ6Lplus evaluation board.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 arch/mips/configs/eyeq6lplus_defconfig | 119 +++++++++++++++++++++++++++++++++
 1 file changed, 119 insertions(+)

diff --git a/arch/mips/configs/eyeq6lplus_defconfig b/arch/mips/configs/eyeq6lplus_defconfig
new file mode 100644
index 000000000000..dc54c3fd1b8a
--- /dev/null
+++ b/arch/mips/configs/eyeq6lplus_defconfig
@@ -0,0 +1,119 @@
+CONFIG_SYSVIPC=y
+CONFIG_NO_HZ_IDLE=y
+CONFIG_HIGH_RES_TIMERS=y
+CONFIG_BPF_SYSCALL=y
+CONFIG_TASKSTATS=y
+CONFIG_IKCONFIG=y
+CONFIG_IKCONFIG_PROC=y
+CONFIG_MEMCG=y
+CONFIG_BLK_CGROUP=y
+CONFIG_CFS_BANDWIDTH=y
+CONFIG_RT_GROUP_SCHED=y
+CONFIG_CGROUP_PIDS=y
+CONFIG_CGROUP_FREEZER=y
+CONFIG_CPUSETS=y
+CONFIG_CGROUP_DEVICE=y
+CONFIG_CGROUP_CPUACCT=y
+CONFIG_NAMESPACES=y
+CONFIG_USER_NS=y
+CONFIG_SCHED_AUTOGROUP=y
+CONFIG_BLK_DEV_INITRD=y
+CONFIG_EXPERT=y
+CONFIG_EYEQ=y
+CONFIG_MACH_EYEQ6LPLUS=y
+CONFIG_MIPS_CPS=y
+CONFIG_CPU_HAS_MSA=y
+CONFIG_NR_CPUS=16
+CONFIG_MIPS_RAW_APPENDED_DTB=y
+CONFIG_JUMP_LABEL=y
+CONFIG_PAGE_SIZE_16KB=y
+CONFIG_COMPAT_32BIT_TIME=y
+CONFIG_MODULES=y
+CONFIG_MODULE_UNLOAD=y
+CONFIG_TRIM_UNUSED_KSYMS=y
+# CONFIG_COMPAT_BRK is not set
+CONFIG_USERFAULTFD=y
+CONFIG_NET=y
+CONFIG_PACKET=y
+CONFIG_UNIX=y
+CONFIG_NET_KEY=y
+CONFIG_INET=y
+CONFIG_IP_PNP=y
+CONFIG_IP_PNP_DHCP=y
+CONFIG_NETFILTER=y
+CONFIG_CAN=y
+CONFIG_PCI=y
+CONFIG_PCI_MSI=y
+CONFIG_PCI_DEBUG=y
+CONFIG_PCI_ENDPOINT=y
+CONFIG_DEVTMPFS=y
+CONFIG_DEVTMPFS_MOUNT=y
+CONFIG_CONNECTOR=y
+CONFIG_MTD=y
+CONFIG_MTD_SPI_NAND=y
+CONFIG_MTD_UBI=y
+CONFIG_MTD_UBI_BLOCK=y
+CONFIG_SCSI=y
+CONFIG_NETDEVICES=y
+CONFIG_MACVLAN=y
+CONFIG_IPVLAN=y
+CONFIG_MACB=y
+CONFIG_MARVELL_PHY=y
+CONFIG_MICREL_PHY=y
+CONFIG_CAN_M_CAN=y
+CONFIG_SERIAL_8250=y
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_HW_RANDOM=y
+CONFIG_I2C=y
+CONFIG_I2C_CHARDEV=y
+CONFIG_I2C_DESIGNWARE_CORE=y
+CONFIG_SPI=y
+CONFIG_SPI_CADENCE_QUADSPI=y
+CONFIG_SPI_DESIGNWARE=y
+CONFIG_SPI_DW_MMIO=y
+CONFIG_SPI_SPIDEV=y
+CONFIG_SPI_SLAVE=y
+# CONFIG_PTP_1588_CLOCK is not set
+CONFIG_PINCTRL=y
+CONFIG_GPIOLIB=y
+CONFIG_GPIO_DWAPB=y
+CONFIG_MFD_SYSCON=y
+CONFIG_HID_A4TECH=y
+CONFIG_HID_BELKIN=y
+CONFIG_HID_CHERRY=y
+CONFIG_HID_CYPRESS=y
+CONFIG_HID_EZKEY=y
+CONFIG_HID_ITE=y
+CONFIG_HID_KENSINGTON=y
+CONFIG_HID_REDRAGON=y
+CONFIG_HID_MICROSOFT=y
+CONFIG_HID_MONTEREY=y
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PLTFM=y
+CONFIG_MMC_SDHCI_CADENCE=y
+# CONFIG_IOMMU_SUPPORT is not set
+CONFIG_RESET_CONTROLLER=y
+# CONFIG_NVMEM is not set
+CONFIG_EXT4_FS=y
+CONFIG_EXT4_FS_POSIX_ACL=y
+CONFIG_EXT4_FS_SECURITY=y
+CONFIG_FS_ENCRYPTION=y
+CONFIG_FUSE_FS=y
+CONFIG_CUSE=y
+CONFIG_MSDOS_FS=y
+CONFIG_VFAT_FS=y
+CONFIG_TMPFS=y
+CONFIG_TMPFS_POSIX_ACL=y
+CONFIG_UBIFS_FS=y
+CONFIG_NFS_FS=y
+CONFIG_NFS_V3_ACL=y
+CONFIG_NFS_V4=y
+CONFIG_NFS_V4_1=y
+CONFIG_NFS_V4_2=y
+CONFIG_ROOT_NFS=y
+CONFIG_FRAME_WARN=1024
+CONFIG_DEBUG_FS=y
+# CONFIG_RCU_TRACE is not set
+# CONFIG_FTRACE is not set

-- 
2.52.0

[PATCH 13/13] MAINTAINERS: Mobileye: Add EyeQ6Lplus files

[Benoît Monin]

Use wildcard to match all EyeQ defconfigs under arch/mips. This covers
the newly added defconfig, and the EyeQ5 and EyeQ6H ones. Add an entry
for the dt-bindings header of the EyeQ6Lplus clocks.

While at it, add myself to the maintainers of Mobileye MIPS SoCs.

Signed-off-by: Benoît Monin <benoit.monin@bootlin.com>
---
 MAINTAINERS | 4 +++-
 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/MAINTAINERS b/MAINTAINERS
index 5b11839cba9d..d9ad70501278 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -17595,6 +17595,7 @@ F:	drivers/media/dvb-frontends/mn88473*
 
 MOBILEYE MIPS SOCS
 M:	Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>
+M:	Benoît Monin <benoit.monin@bootlin.com>
 M:	Gregory CLEMENT <gregory.clement@bootlin.com>
 M:	Théo Lebrun <theo.lebrun@bootlin.com>
 L:	linux-mips@vger.kernel.org
@@ -17602,12 +17603,13 @@ S:	Maintained
 F:	Documentation/devicetree/bindings/mips/mobileye.yaml
 F:	Documentation/devicetree/bindings/soc/mobileye/
 F:	arch/mips/boot/dts/mobileye/
-F:	arch/mips/configs/eyeq5_defconfig
+F:	arch/mips/configs/eyeq*_defconfig
 F:	arch/mips/mobileye/board-epm5.its.S
 F:	drivers/clk/clk-eyeq.c
 F:	drivers/pinctrl/pinctrl-eyeq5.c
 F:	drivers/reset/reset-eyeq.c
 F:	include/dt-bindings/clock/mobileye,eyeq5-clk.h
+F:	include/dt-bindings/clock/mobileye,eyeq6lplus-clk.h
 
 MODULE SUPPORT
 M:	Luis Chamberlain <mcgrof@kernel.org>

-- 
2.52.0

Re: [PATCH 00/13] Introducing the Mobileye EyeQ6Lplus SoC

[Linus Walleij]

Hi Benoit,

thanks for your patches!

On Wed, Dec 17, 2025 at 2:36 PM Benoît Monin <benoit.monin@bootlin.com> wrote:

> The Eyeq6Lplus is a new system-on-chip part of Mobileye's EyeQ family

I don't know if this is "new" since it was announced in 2022.

> of SoC aimed at Advanced Driver Assistance Systems (ADAS). It is built
> around a multicore MIPS I6500 with 2 cores and 8 threads and integrates
> controllers and accelerators dedicated to driving assistance.

I think a question on everyone's lips is how much new MIPS hardware
MobilEye are going to be churning out? Is there *more* coming?

Don't get me wrong - I think it is pretty cool. But as these systems have
long support cycles, this will have direct consequences for the MIPS arch
maintenance and longevity.

Yours,
Linus Walleij

Re: [PATCH 00/13] Introducing the Mobileye EyeQ6Lplus SoC

[Benoît Monin]

Hi Linus,

On 12/19/25 13:03, Linus Walleij wrote:
> Hi Benoit,
> 
> thanks for your patches!
> 
> On Wed, Dec 17, 2025 at 2:36 PM Benoît Monin <benoit.monin@bootlin.com> wrote:
> 
>> The Eyeq6Lplus is a new system-on-chip part of Mobileye's EyeQ family
> 
> I don't know if this is "new" since it was announced in 2022.
> 
The EyeQ6L family was announced in 2024[1] and this particular variant,
the EyeQ6Lplus, is from this year I guess.

>> of SoC aimed at Advanced Driver Assistance Systems (ADAS). It is built
>> around a multicore MIPS I6500 with 2 cores and 8 threads and integrates
>> controllers and accelerators dedicated to driving assistance.
> 
> I think a question on everyone's lips is how much new MIPS hardware
> MobilEye are going to be churning out? Is there *more* coming?
> 
I cannot say for sure what are Mobileye plans but the next platform
we are working on is based on RISC-V, with MIPS P8700 cores[2]. 

> Don't get me wrong - I think it is pretty cool. But as these systems have
> long support cycles, this will have direct consequences for the MIPS arch
> maintenance and longevity.
> 
> Yours,
> Linus Walleij

[1]: https://www.mobileye.com/news/mobileye-eyeq6-lite-launches-to-speed-adas-upgrades-worldwide/
[2]: https://mips.com/products/hardware/p8700/