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Thu, 20 Aug 2026 19:50:17 -0700 (PDT) Received: from Turin ([187.15.143.241]) by smtp.gmail.com with ESMTPSA id 956f58d0204a3-66ccb144956sm3682195d50.13.2026.08.20.19.50.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 20 Aug 2026 19:50:16 -0700 (PDT) From: Nicholas Dudar To: ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, eddyz87@gmail.com, memxor@gmail.com, johan.almbladh@anyfinetworks.com, paulburton@kernel.org, tsbogend@alpha.franken.de Cc: martin.lau@linux.dev, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, emil@etsalapatis.com, ihor.solodrai@linux.dev, bpf@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [RFC bpf-next 0/2] bpf, mips: Add BPF_MEMSX support to the JITs Date: Thu, 20 Aug 2026 22:46:38 -0400 Message-ID: <20260821024640.1601299-1-main.kalliope@gmail.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit bpf-next is closed for the merge window, so I am sending this for review. I plan to post this series after it reopens. The MIPS32 and MIPS64 JITs reject BPF_MEMSX byte, half-word, and word instructions, so a program containing one cannot run when JIT execution is required. First factor ordinary narrow-load selection into backend-local helpers. Then extend those helpers to select signed native loads for BPF_MEMSX. MIPS32 observes the load-delay rule and propagates the low-word sign into the high half; MIPS64 obtains the full result from the native load. Ordinary loads remain unsigned, and BPF_MEMSX with BPF_DW remains unsupported. This series must be applied after the in-review MIPS MOVSX and SDIV/SMOD series: MOVSX: https://lore.kernel.org/bpf/20260819010523.1057789-1-main.kalliope@gmail.com/ SDIV/SMOD: https://lore.kernel.org/bpf/20260810194215.3754591-1-main.kalliope@gmail.com/ Applying MEMSX removes a whole-program JIT fallback that otherwise keeps mixed programs containing unsupported MOVSX or signed DIV/MOD out of the JIT. The ordering discussion is here: https://lore.kernel.org/bpf/CAJZwKkis=3NGw9At0WfiZaRYEoMPbQfqJKN0e+vtRDvp4VY5Ng@mail.gmail.com/ On four little-endian profiles, patch 1 leaves the complete test_bpf results with 1031 passed/31 failed on MIPS32 and 1030/31 on MIPS64. Patch 2 changes the three MEMSX cases, yielding 1034/28 and 1033/28, respectively. Ordinary unsigned-load controls passed at each boundary. Selector-focused QEMU testing covered MIPS32 base, R2, and R6 plus pre-R6 MIPS64, each in big- and little-endian configurations. The focused mixed-operation matrix reproduced the unsafe MEMSX-first ordering and the correct fully composed result on MIPS32 and MIPS64, both big- and little-endian. No physical MIPS hardware was tested. Nicholas Dudar (2): bpf, mips: Factor narrow loads out of emit_ldx() bpf, mips: Add BPF_MEMSX support to the JITs arch/mips/net/bpf_jit_comp32.c | 51 ++++++++++++++++++++++++++++------ arch/mips/net/bpf_jit_comp64.c | 47 +++++++++++++++++++++++++++---- 2 files changed, 85 insertions(+), 13 deletions(-) base-commit: 91ec2035134982b98fab0609a9fd8480e8217dc1 prerequisite-patch-id: aa8ca3f50fc4b0160c5fdba43a92e4b7ec3f2e07 prerequisite-patch-id: bda4c3f3d59b48d784ed98bd8558d9591399bc86 prerequisite-patch-id: 35236f563c0536859077709d52b345b696e5c26e prerequisite-patch-id: c0f282b0e57ecd60e9582fb1e89e4b3112ae7893 prerequisite-patch-id: 4e93eed38f6585e21fc13931c314907b4e437ef5