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Tue, 15 Sep 2026 00:13:18 -0700 (PDT) Received: from center.jhjvjihww5qejoy14qwv1cc4td.frax.internal.cloudapp.net ([131.189.143.225]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-49e7d284a7bsm117889265e9.3.2026.09.15.00.13.18 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 15 Sep 2026 00:13:18 -0700 (PDT) From: Orgad Shaneh To: tsbogend@alpha.franken.de Cc: linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH 5/5] MIPS: OCTEON: require the Core-14449 workaround only on CN63XX pass 1 Date: Tue, 15 Sep 2026 07:12:48 +0000 Message-ID: <20260915071306.15006-5-orgads@gmail.com> X-Mailer: git-send-email 2.47.3 In-Reply-To: <20260915071306.15006-1-orgads@gmail.com> References: <20260915071306.15006-1-orgads@gmail.com> Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit prom_free_prom_memory() probes the hint field of a compiler-emitted PREF and panics when it is not 28, which is what -Wa,-mfix-cn63xxp1 (CONFIG_CAVIUM_CN63XXP1) rewrites every prefetch in the kernel to. The test is gated on OCTEON_IS_MODEL(OCTEON_CN6XXX), so it fires on every OCTEON II part, including the pass 2 chips that do not need the workaround: Kernel panic - not syncing: OCTEON II DCache prefetch workaround not in place (cfa00004). Please build kernel with proper options (CONFIG_CAVIUM_CN63XXP1). on a CN6335-AAP pass 2.2. Core-14449 is a CN63XX pass 1.x erratum, and the vendor's own runtime check says so: it errors out only for OCTEON_CN63XX_PASS1_X without the fix, and otherwise merely warns about lost performance when fixed code runs on a part that is not a CN63XX. Narrow the check to CN63XX pass 1.x to match. The alternative - enabling CONFIG_CAVIUM_CN63XXP1 to satisfy the check - is not free: the assembler flag rewrites every prefetch in the kernel (77 of them in this build) to pref 0x1c, which is worth avoiding on an in-order core whose receive path is dominated by memcpy. uasm_i_pref() keeps its OCTEON_CN6XXX condition: it only touches the handful of runtime-generated TLB handlers, where the cost does not matter. Assisted-by: Claude:claude-opus-5 Signed-off-by: Orgad Shaneh --- diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c --- a/arch/mips/cavium-octeon/setup.c +++ b/arch/mips/cavium-octeon/setup.c @@ -1127,7 +1127,7 @@ EXPORT_SYMBOL(prom_putchar); void __init prom_free_prom_memory(void) { - if (OCTEON_IS_MODEL(OCTEON_CN6XXX)) { + if (OCTEON_IS_MODEL(OCTEON_CN63XX_PASS1_X)) { /* Check for presence of Core-14449 fix. */ u32 insn; u32 *foo; -- 2.47.0