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[90.182.112.124]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a359fbc718sm154241835e9.2.2026.10.26.03.00.09 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 26 Oct 2026 03:00:10 -0700 (PDT) Date: Mon, 26 Oct 2026 11:00:08 +0100 From: Joshua Crofts To: Olivier Louvignes Cc: Jonathan Cameron , David Lechner , Nuno =?ISO-8859-1?Q?S=E1?= , Andy Shevchenko , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Cercueil , "H . Nikolaus Schaller" , linux-iio@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 2/2] iio: adc: Add a driver for the Ingenic X1600 ADC Message-ID: <20261026110008.00005296@gmail.com> In-Reply-To: <20261026083631.48406-3-olivier@mgcrea.io> References: <20261026083631.48406-1-olivier@mgcrea.io> <20261026083631.48406-3-olivier@mgcrea.io> X-Mailer: Claws Mail 4.4.0 (GTK 3.24.51; x86_64-w64-mingw32) X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 26 Oct 2026 09:36:31 +0100 Olivier Louvignes wrote: > The X1600's SAR ADC has four auxiliary channels, each with its own start > bit, interrupt flag and 12-bit result, and none of the touchscreen or > battery engines of the JZ47xx ADCs that ingenic-adc drives. Add a small > driver that exposes the four channels as voltages against the 3.3 V > reference. > > The registers are in chapter 19 of the X1600 programming manual. The > ADC clock divider is even, as the manual has it (an odd value divides > by one less); the vendor kernel writes the divider minus one, which > gives a slightly faster clock than it asks for. > > Tested on a HiBy R1, whose play/pause and volume keys sit on channel 0 > behind adc-keys: all three read and report correctly. > > Signed-off-by: Olivier Louvignes > --- The driver looks good to me now! Reviewed-by: Joshua Crofts -- Kind regards, Joshua Crofts