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Sun, 08 Nov 2026 13:57:46 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b1152fa888sm5692976a91.9.2026.11.08.13.57.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 13:57:45 -0800 (PST) From: Rosen Penev To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Alban Bedel Cc: Radu Rendec , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 0/3] ath79: flush every write buffer of a shared CPU interrupt Date: Sun, 8 Nov 2026 13:57:35 -0800 Message-ID: <20261108215738.113582-1-rosenp@gmail.com> X-Mailer: git-send-email 2.56.0 X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On AR934x and QCA953x, the WMAC and the PCIe root complex share CPU interrupt 2, but each writes to DDR through its own write buffer in the DDR controller. The ath79 CPU interrupt controller flushes one write buffer per interrupt before running its handlers, so only the buffer listed last in the device tree gets flushed, and the other device can read stale descriptors. Patch 1 documents in the binding that a CPU interrupt may be listed once per write buffer. Patch 2 keeps a mask of write buffers per CPU interrupt and flushes all of them, and documents how the interrupt lines, the write buffers and the flush fit together. Patch 3, suggested by Thomas, starts the flushes of all the buffers of an interrupt before waiting for any of them, so they drain in parallel, and replaces the "It must be run twice" comment with what the AR7100 datasheet says about it. Patch 3 changes the signature of ath79_ddr_wb_flush() and its call site in the irqchip driver, so patches 2 and 3 should go through the same tree. Changes since v1: - Add dt-binding change. - Add a comment describing the interrupt wiring and the write buffers (Thomas) - New patch 3: flush the write buffers of an interrupt in parallel, and document the double flush from the AR7100 datasheet (Thomas) Build tested with ath79_defconfig (LLVM, W=1). Claude Code (Claude Opus 5.5) helped write the comments, patch 3 and the commit messages, and searched the Atheros datasheets for the double-flush requirement. I reviewed all the changes. Rosen Penev (3): dt-bindings: interrupt-controller: qca,ar7100-cpu-intc: allow shared write buffer interrupts irqchip/ath79-cpu: flush every write buffer of a shared interrupt MIPS: ath79: flush the DDR write buffers of an interrupt in parallel .../qca,ar7100-cpu-intc.yaml | 5 +- arch/mips/ath79/common.c | 51 ++++++++++++++----- arch/mips/include/asm/mach-ath79/ath79.h | 2 +- drivers/irqchip/irq-ath79-cpu.c | 44 ++++++++++------ 4 files changed, 73 insertions(+), 29 deletions(-) -- 2.56.0