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Sun, 08 Nov 2026 13:57:48 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b1152fa888sm5692976a91.9.2026.11.08.13.57.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 13:57:47 -0800 (PST) From: Rosen Penev To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thomas Bogendoerfer , Alban Bedel Cc: Radu Rendec , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: interrupt-controller: qca,ar7100-cpu-intc: allow shared write buffer interrupts Date: Sun, 8 Nov 2026 13:57:36 -0800 Message-ID: <20261108215738.113582-2-rosenp@gmail.com> X-Mailer: git-send-email 2.56.0 In-Reply-To: <20261108215738.113582-1-rosenp@gmail.com> References: <20261108215738.113582-1-rosenp@gmail.com> X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit On AR934x and QCA953x, the WMAC and the PCIe root complex share CPU interrupt 2, but write to DDR through different write buffers. Document that such an interrupt is listed once for each write buffer, and that all of them are flushed. Signed-off-by: Rosen Penev --- .../bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml index ab32a91af4c4..becec88061d7 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/qca,ar7100-cpu-intc.yaml @@ -29,7 +29,10 @@ properties: const: 1 qca,ddr-wb-channel-interrupts: - description: List of interrupts needing a write buffer flush + description: + List of interrupts needing a write buffer flush. An interrupt shared by + several devices that use different write buffers is listed once for + each of them, and all of their write buffers are flushed. $ref: /schemas/types.yaml#/definitions/uint32-array qca,ddr-wb-channels: -- 2.56.0