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Thu, 12 Nov 2026 14:45:07 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id 98e67ed59e1d1-3b1b3b708adsm37073a91.4.2026.11.12.14.45.04 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 12 Nov 2026 14:45:06 -0800 (PST) From: Rosen Penev To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Bogendoerfer , Thomas Gleixner Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Radu Rendec , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH 0/4] irqchip/ath79-misc: probe as a platform driver Date: Thu, 12 Nov 2026 14:44:41 -0800 Message-ID: <20261112224445.213324-1-rosenp@gmail.com> X-Mailer: git-send-email 2.56.1 X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The MISC interrupt controller of the Atheros/Qualcomm ath79 SoCs is cascaded from a CPU interrupt, and all of its users are platform devices. It is still initialized from IRQCHIP_DECLARE, before the early initcalls, only because the MIPS perf code asks for the performance counter overflow interrupt, which goes through it, from an early_initcall. Patch 1 makes the MIPS perf code look up that interrupt when the first event is created, which is when it is requested. Patch 2 makes the ath79 MISC driver create the mapping at that point. Patch 3 then converts the driver to IRQCHIP_PLATFORM_DRIVER with device-managed resources, which also fixes the leak of the register mapping on its error path. Patch 4 adds COMPILE_TEST coverage, which a platform driver makes possible. Patch 3 depends on patch 1: without it, perf would ask for the interrupt before the controller has probed and would lose its overflow interrupt. Patch 1 touches only arch/mips, so the series could go through the MIPS tree with an ack for the irqchip patches, or through irqchip with an ack for patch 1. The other users of get_c0_perfcount_int() (generic/GIC, Malta, Lantiq, Ralink) return an interrupt that is set up at boot, so calling it later does not change anything for them. The perf boot message no longer prints the interrupt, which is not known at that point. Tested on a TP-Link Archer C7 v2 (QCA9558), with the device tree from the pending series that adds it: the MISC controller probes as a platform device, its users (UART, GPIO, watchdog) probe with nothing left deferred, and perf record gets its samples from the overflow interrupt on MISC 5. Each patch builds with W=1 (mips, clang), and with patch 4 the driver also builds with W=1 for arm64, x86_64 and a non-ath79 MIPS kernel (Lantiq). An AI coding assistant (Claude Code, Claude Opus 5.5) was used to write the patches, test them on the router over its serial console, and draft the commit messages and this cover letter. Rosen Penev (4): MIPS: perf: look up the PMU interrupt when it is requested irqchip/ath79-misc: map the performance counter interrupt on demand irqchip/ath79-misc: convert to a platform driver irqchip/ath79-misc: allow COMPILE_TEST builds arch/mips/kernel/perf_event_mipsxx.c | 30 +++++--- drivers/irqchip/Kconfig | 14 ++++ drivers/irqchip/Makefile | 2 +- drivers/irqchip/irq-ath79-misc.c | 108 ++++++++++++++------------- 4 files changed, 88 insertions(+), 66 deletions(-) base-commit: aaa2f954c21b205a0bcd0961e5b2be4e82e58455 -- 2.56.1