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Fri, 13 Nov 2026 10:42:56 -0800 (PST) Received: from eldorado ([2600:8802:b00:1f88::287]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1b50316e195sm10526177c88.8.2026.11.13.10.42.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 10:42:55 -0800 (PST) From: Florian Fainelli To: linux-mips@vger.kernel.org Cc: Florian Fainelli , stable@vger.kernel.org, Paul Cercueil , Thomas Bogendoerfer , Paul Burton , Stephen Boyd , Brian Masney , Jerome Brunet , =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= , Jiaxun Yang , linux-kernel@vger.kernel.org (open list), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), hns@goldelico.com, paul@boddie.org.uk Subject: [PATCH v5 1/4] clk: ingenic: Poll JZ4780 CPU1 power status atomically Date: Fri, 13 Nov 2026 10:42:07 -0800 Message-ID: <20261113184210.470320-2-f.fainelli@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261113184210.470320-1-f.fainelli@gmail.com> References: <20261113184210.470320-1-f.fainelli@gmail.com> X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit The CPU1 clock enable callback runs under the clock framework's spinlock with interrupts disabled. Its readl_poll_timeout() can sleep between reads, which is invalid in this context when SMP powers up CPU1. Use readl_poll_timeout_atomic() with the existing interval and timeout. This is a prerequisite for the JZ4780 SMP bring-up path. The original CPU1 clock implementation by Zhou Yanjie is already upstream. Cross-built for CI20; the subsequent SMP-enabled image brought up both CPU cores. Development and validation used Codex assistance. CC: stable@vger.kernel.org Fixes: 6673db4f3f26 ("clk: JZ4780: Add function for enable the second core.") Link: https://lkml.kernel.org/r/1582215889-113034-3-git-send-email-zhouyanjie@wanyeetech.com Reviewed-by: Paul Cercueil Tested-by: Paul Cercueil Signed-off-by: Florian Fainelli --- Changes since previous posting: - No changes to this patch. drivers/clk/ingenic/jz4780-cgu.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/clk/ingenic/jz4780-cgu.c b/drivers/clk/ingenic/jz4780-cgu.c index 1e88aef7ac0f..1809f8859c7e 100644 --- a/drivers/clk/ingenic/jz4780-cgu.c +++ b/drivers/clk/ingenic/jz4780-cgu.c @@ -242,8 +242,8 @@ static int jz4780_core1_enable(struct clk_hw *hw) spin_unlock_irqrestore(&cgu->lock, flags); /* wait for the CPU to be powered up */ - retval = readl_poll_timeout(cgu->base + CGU_REG_LCR, lcr, - !(lcr & LCR_SCPUS), 10, timeout); + retval = readl_poll_timeout_atomic(cgu->base + CGU_REG_LCR, lcr, + !(lcr & LCR_SCPUS), 10, timeout); if (retval == -ETIMEDOUT) { pr_err("%s: Wait for power up core1 timeout\n", __func__); return retval;