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Fri, 13 Nov 2026 11:08:43 -0800 (PST) Received: from eldorado ([2600:8802:b00:1f88::287]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-379569b8389sm15714037eec.25.2026.11.13.11.08.42 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 13 Nov 2026 11:08:42 -0800 (PST) From: Florian Fainelli To: linux-mips@vger.kernel.org Cc: Florian Fainelli , Thomas Bogendoerfer , Paul Burton , Paul Cercueil , Stephen Boyd , Brian Masney , Jerome Brunet , =?UTF-8?q?=E5=91=A8=E7=90=B0=E6=9D=B0=20=28Zhou=20Yanjie=29?= , Jiaxun Yang , linux-kernel@vger.kernel.org (open list), linux-clk@vger.kernel.org (open list:COMMON CLK FRAMEWORK), hns@goldelico.com, paul@boddie.org.uk Subject: [PATCH v6 2/4] MIPS: Skip generic IPI setup for platform-specific callbacks Date: Fri, 13 Nov 2026 11:08:34 -0800 Message-ID: <20261113190836.470937-3-f.fainelli@gmail.com> X-Mailer: git-send-email 2.53.0 In-Reply-To: <20261113190836.470937-1-f.fainelli@gmail.com> References: <20261113190836.470937-1-f.fainelli@gmail.com> X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit A generic MIPS kernel can select a platform SMP backend with direct IPI callbacks instead of an IPI IRQ domain. The XBurst backend uses CP0 mailboxes, so generic IPI allocation would find no domain and BUG when more than one CPU is present. Skip generic IPI initialization when neither selected send callback uses the generic implementation. Keep initialization when either callback uses generic IRQ IPIs, and retain the existing single-CPU shortcut. Sashiko AI reported the XBurst integration issue; Codex assisted with the change and extracted-function/build checks. Signed-off-by: Florian Fainelli --- Changes in v6: - addded missing Signed-off-by tag Changes since previous posting: - Split the generic IPI initialization guard out of the XBurst SMP patch as a prerequisite, as requested by Paul Cercueil. - Add braces around the multi-line condition. arch/mips/kernel/smp.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/arch/mips/kernel/smp.c b/arch/mips/kernel/smp.c index 0f28b4a62e72..086298146dd8 100644 --- a/arch/mips/kernel/smp.c +++ b/arch/mips/kernel/smp.c @@ -338,8 +338,12 @@ int mips_smp_ipi_free(const struct cpumask *mask) static int __init mips_smp_ipi_init(void) { - if (num_possible_cpus() == 1) + /* Platforms with their own IPI callbacks do not need an IRQ domain. */ + if ((mp_ops->send_ipi_single != mips_smp_send_ipi_single && + mp_ops->send_ipi_mask != mips_smp_send_ipi_mask) || + num_possible_cpus() == 1) { return 0; + } mips_smp_ipi_allocate(cpu_possible_mask);