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Sat, 14 Nov 2026 15:37:27 -0800 (PST) Received: from ryzen.lan ([2601:644:8000:37f::e34]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8bed2d0f473sm2306372b3a.53.2026.11.14.15.37.24 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 14 Nov 2026 15:37:26 -0800 (PST) From: Rosen Penev To: Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Thomas Bogendoerfer , Thomas Gleixner Cc: Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Radu Rendec , linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Subject: [PATCH v2 1/4] MIPS: perf: look up the PMU interrupt when it is requested Date: Sat, 14 Nov 2026 15:37:15 -0800 Message-ID: <20261114233718.86520-2-rosenp@gmail.com> X-Mailer: git-send-email 2.56.1 In-Reply-To: <20261114233718.86520-1-rosenp@gmail.com> References: <20261114233718.86520-1-rosenp@gmail.com> X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Transfer-Encoding: 8bit init_hw_perf_events() is an early_initcall and asks the platform for the counter overflow interrupt through get_c0_perfcount_int(). On ath79, that interrupt goes through the MISC interrupt controller, so the controller has to be initialized from IRQCHIP_DECLARE before the early initcalls, even though nothing else needs it that early. The interrupt is only requested when the first event is created. Look it up then, so that it can come from an interrupt controller probed as a platform driver. The boot message no longer prints the interrupt. Signed-off-by: Rosen Penev --- arch/mips/kernel/perf_event_mipsxx.c | 30 +++++++++++++++++----------- 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/arch/mips/kernel/perf_event_mipsxx.c b/arch/mips/kernel/perf_event_mipsxx.c index 196a070349b0..4d660952e643 100644 --- a/arch/mips/kernel/perf_event_mipsxx.c +++ b/arch/mips/kernel/perf_event_mipsxx.c @@ -589,10 +589,25 @@ static atomic_t active_events = ATOMIC_INIT(0); static DEFINE_MUTEX(pmu_reserve_mutex); static int (*save_perf_irq)(void); +/* + * The interrupt is looked up when the first event is created, not when the + * PMU is registered: on some platforms, the interrupt controller that the + * counter overflow is wired to is only probed after the early initcalls. + */ +static int mipspmu_find_irq(void) +{ + if (get_c0_perfcount_int) + return get_c0_perfcount_int(); + if (cp0_perfcount_irq >= 0) + return MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; + return -1; +} + static int mipspmu_get_irq(void) { int err; + mipspmu.irq = mipspmu_find_irq(); if (mipspmu.irq >= 0) { /* Request my own irq handler. */ err = request_irq(mipspmu.irq, mipsxx_pmu_handle_irq, @@ -1889,7 +1904,7 @@ static const struct mips_perf_event *octeon_pmu_map_raw_event(u64 config) static int __init init_hw_perf_events(void) { - int counters, irq, pmu_type; + int counters, pmu_type; pr_info("Performance counters: "); @@ -1904,13 +1919,6 @@ init_hw_perf_events(void) counters = counters_total_to_per_cpu(counters); #endif - if (get_c0_perfcount_int) - irq = get_c0_perfcount_int(); - else if (cp0_perfcount_irq >= 0) - irq = MIPS_CPU_IRQ_BASE + cp0_perfcount_irq; - else - irq = -1; - mipspmu.map_raw_event = mipsxx_pmu_map_raw_event; switch (current_cpu_type()) { @@ -2017,7 +2025,6 @@ init_hw_perf_events(void) } mipspmu.num_counters = counters; - mipspmu.irq = irq; if (read_c0_perfctrl0() & MIPS_PERFCTRL_W) { if (get_loongson3_pmu_type() == LOONGSON_PMU_TYPE2) { @@ -2044,9 +2051,8 @@ init_hw_perf_events(void) on_each_cpu(reset_counters, (void *)(long)counters, 1); - pr_cont("%s PMU enabled, %d %d-bit counters available to each " - "CPU, irq %d%s\n", mipspmu.name, counters, counter_bits, irq, - irq < 0 ? " (share with timer interrupt)" : ""); + pr_cont("%s PMU enabled, %d %d-bit counters available to each CPU\n", + mipspmu.name, counters, counter_bits); perf_pmu_register(&pmu, "cpu", PERF_TYPE_RAW); -- 2.56.1