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In-Reply-To: <D0H7PXOXYNXI.2QM4E0O02FK34@bootlin.com>
References: <20240410-mbly-olb-v1-0-335e496d7be3@bootlin.com> <20240410-mbly-olb-v1-4-335e496d7be3@bootlin.com> <4ce9f3cea1ecd3777cf3e291cc865210.sboyd@kernel.org> <D0H7PXOXYNXI.2QM4E0O02FK34@bootlin.com>
Subject: Re: [PATCH 04/11] clk: divider: Introduce CLK_DIVIDER_EVEN_INTEGERS flag
From: Stephen Boyd <sboyd@kernel.org>
Cc: linux-mips@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, Vladimir Kondratiev <vladimir.kondratiev@mobileye.com>, Gregory CLEMENT <gregory.clement@bootlin.com>, Thomas Petazzoni <thomas.petazzoni@bootlin.com>, Tawfik Bayouk <tawfik.bayouk@mobileye.com>
To: Conor Dooley <conor+dt@kernel.org>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@linaro.org>, Linus Walleij <linus.walleij@linaro.org>, Michael Turquette <mturquette@baylibre.com>, Philipp Zabel <p.zabel@pengutronix.de>, Rob Herring <robh@kernel.org>, =?utf-8?q?Th=C3=A9o?= Lebrun <theo.lebrun@bootlin.com>
Date: Thu, 11 Apr 2024 22:19:49 -0700
User-Agent: alot/0.10

Quoting Th=C3=A9o Lebrun (2024-04-11 03:14:09)
> Hello,
>=20
> On Thu Apr 11, 2024 at 5:06 AM CEST, Stephen Boyd wrote:
> > Quoting Th=C3=A9o Lebrun (2024-04-10 10:12:33)
> > > index 4a537260f655..cb348e502e41 100644
> > > --- a/include/linux/clk-provider.h
> > > +++ b/include/linux/clk-provider.h
> > > @@ -675,13 +675,15 @@ struct clk_div_table {
> > >   * CLK_DIVIDER_BIG_ENDIAN - By default little endian register access=
es are used
> > >   *     for the divider register.  Setting this flag makes the regist=
er accesses
> > >   *     big endian.
> > > + * CLK_DIVIDER_EVEN_INTEGERS - clock divisor is 2, 4, 6, 8, 10, etc.
> > > + *     Formula is 2 * (value read from hardware + 1).
> > >   */
> > >  struct clk_divider {
> > >         struct clk_hw   hw;
> > >         void __iomem    *reg;
> > >         u8              shift;
> > >         u8              width;
> > > -       u8              flags;
> > > +       u16             flags;
> >
> > This can stay u8
>=20
> It is unclear to me why it can stay u8? __clk_hw_register_divider() puts
> clk_divider_flags into flags field of struct clk_divider.
> BIT(8) overflows u8.

Oh, I missed that part.

>=20
> >
> > >         const struct clk_div_table      *table;
> > >         spinlock_t      *lock;
> > >  };
> >
> > We should add a kunit test.
>=20
> Will look into how this works and try something for next revision. I
> guess you are talking about adding clk_divider tests, not only tests
> for this flag? I cannot find any existing kunit tests for clk_divider.
>=20

Right, there aren't any tests today. Thanks.