RM7000 cache question

[Pete Popov <ppopov@mvista.com>]

Question on the RM7000 caches:

The function __flush_cache_all_d32i32() (and some other ones), flush the
entire primary data cache using blast_dache32().  Since writebacks from
the primary cache go to the secondary and tertiary/main memory, this
function seems fine. However, blast_dcache32() uses indexed cache
instructions. The primary data cache is only 16KB; the secondary cache
is 256KB. So my question is, since we're using indexed instructions, and
the primary data cache is only 16KB, will that flush only one of the 4
ways of the secondary cache, since each way is 64KB?  

static void __flush_cache_all_d32i32(void)
{
        blast_dcache32();
        blast_icache32();
}                              


Pete