From: Jun Sun <jsun@mvista.com>
To: "Kevin D. Kissell" <kevink@mips.com>
Cc: carlson@sibyte.com, Matthew Dharm <mdharm@momenco.com>,
linux-mips@oss.sgi.com
Subject: Re: Multiple processor support?
Date: Mon, 26 Mar 2001 11:20:35 -0800 [thread overview]
Message-ID: <3ABF9683.1D08617B@mvista.com> (raw)
In-Reply-To: 01b801c0b3fb$1770b740$0deca8c0@Ulysses
"Kevin D. Kissell" wrote:
>
> (Software cache coherency) It is possible,
> but tricky, and at times unavoidably inefficient to build a
> software-coherent SMP system. I have not heard of anyone
> doing so with MIPS/Linux.
>
How would it be possible? Any reference to the previous implementations?
I imagine you would need at least some kind of atomic operation (like ll/sc)
working reliably (which itself may require cache coherency). Also, any such
scheme should not require massive change in the programming.
I am very curious....
Jun
next prev parent reply other threads:[~2001-03-26 19:25 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-03-23 22:53 Multiple processor support? Matthew Dharm
2001-03-23 22:58 ` Justin Carlson
2001-03-24 0:01 ` Matthew Dharm
2001-03-24 0:01 ` Matthew Dharm
2001-03-24 0:08 ` Justin Carlson
2001-03-24 0:08 ` Justin Carlson
2001-03-24 0:29 ` Keith M Wesolowski
2001-03-24 0:40 ` Kevin D. Kissell
2001-03-24 0:40 ` Kevin D. Kissell
2001-03-24 1:23 ` Ralf Baechle
2001-03-24 1:23 ` Ralf Baechle
2001-03-26 19:20 ` Jun Sun [this message]
2001-03-29 9:16 ` Kevin D. Kissell
2001-03-29 9:16 ` Kevin D. Kissell
2001-03-24 0:13 ` Joe George
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