[PATCH] pci_auto handles better when no IO/MEM behind P2P bridge

[Jun Sun <jsun@mvista.com>]

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Any objections?

Jun

[-- Attachment #2: pci-auto-p2p-bridge-noiomem.011205.011206.patch --]
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diff -Nru test/arch/mips/kernel/pci_auto.c.orig test/arch/mips/kernel/pci_auto.c
--- test/arch/mips/kernel/pci_auto.c.orig	Mon Nov 26 18:22:58 2001
+++ test/arch/mips/kernel/pci_auto.c	Thu Dec  6 18:05:04 2001
@@ -252,9 +252,28 @@
 			      int top_bus,
 			      int current_bus,
 			      int pci_devfn,
-			      int sub_bus)
+			      int sub_bus,
+			      u32 prescan_pciauto_lower_iospc,
+			      u32 prescan_pciauto_lower_memspc)
 {
 	u32 temp;
+	u32 flag;
+
+	/* 
+	 * [jsun] we cannot simply just write post scan value.
+	 * If there is nothing behind P2P bridge, we need to 
+	 * turn off the IO/MEM addr decoding at all. 
+	 * The spec recommands to write higher BASE value than the LIMIT
+	 * value.  I think it works just fine if we disable appropriate
+	 * bits in COMMAND register.
+	 */
+	flag = PCI_COMMAND_MASTER;
+	if (prescan_pciauto_lower_memspc != pciauto_lower_memspc) {
+		flag |= PCI_COMMAND_MEMORY;
+	}
+	if (prescan_pciauto_lower_iospc != pciauto_lower_iospc) {
+		flag |= PCI_COMMAND_IO;
+	}
 
 	/* Configure bus number registers */
 	early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
@@ -278,8 +297,7 @@
 	early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
 		PCI_COMMAND, &temp);
 	early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
-		PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
-		| PCI_COMMAND_MASTER);
+		PCI_COMMAND, temp | flag);
 }
 
 #define      PCIAUTO_IDE_MODE_MASK           0x05
@@ -331,6 +349,9 @@
 		DBG("\n");
 
 		if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
+			u32 prescan_pciauto_lower_iospc;
+			u32 prescan_pciauto_lower_memspc;
+
 			DBG("        Bridge: primary=%.2x, secondary=%.2x\n",
 				current_bus, sub_bus + 1);
 			pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
@@ -338,10 +359,16 @@
 			DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
 				sub_bus + 1,
 				pciauto_lower_iospc, pciauto_lower_memspc);
+
+			prescan_pciauto_lower_iospc = pciauto_lower_iospc;
+			prescan_pciauto_lower_memspc = pciauto_lower_memspc;
+
 			sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
 			DBG("Back to bus %.2x\n", current_bus);
 			pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
-						      pci_devfn, sub_bus);
+						      pci_devfn, sub_bus,
+						      prescan_pciauto_lower_iospc,
+						      prescan_pciauto_lower_memspc);
 			continue;
 		} else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {