--- arch/mips/mm/c-mips32.c Wed May 29 05:03:17 2002 +++ ../../linux-2.4.18/sw/linux-2.4.18/arch/mips/mm/c-mips32.c Thu Jul 11 09:55:08 2002 @@ -17,7 +17,6 @@ * * MIPS32 CPU variant specific MMU/Cache routines. */ -#include #include #include #include @@ -75,7 +74,8 @@ unsigned long flags; __save_and_cli(flags); - blast_dcache(); blast_icache(); + blast_dcache(); + blast_icache(); __restore_flags(flags); } @@ -303,7 +303,7 @@ if (!(vma->vm_flags & VM_EXEC)) return; - address = KSEG0 + ((unsigned long)page_address(page) & PAGE_MASK & (dcache_size - 1)); + address = KSEG0 + ((unsigned long)page_address(page) & PAGE_MASK & (icache_size - 1)); blast_icache_page_indexed(address); } @@ -317,7 +317,7 @@ unsigned int flags; if (size >= dcache_size) { - flush_cache_all(); + blast_dcache(); } else { __save_and_cli(flags); a = addr & ~(dc_lsize - 1); @@ -338,7 +338,7 @@ unsigned long end, a; if (size >= scache_size) { - flush_cache_all(); + blast_scache(); return; } @@ -358,13 +358,13 @@ unsigned int flags; if (size >= dcache_size) { - flush_cache_all(); + blast_dcache(); } else { __save_and_cli(flags); a = addr & ~(dc_lsize - 1); end = (addr + size) & ~(dc_lsize - 1); while (1) { - flush_dcache_line(a); /* Hit_Writeback_Inv_D */ + invalidate_dcache_line(a); /* Hit_Inv_D */ if (a == end) break; a += dc_lsize; } @@ -380,14 +380,14 @@ unsigned long end, a; if (size >= scache_size) { - flush_cache_all(); + blast_scache(); return; } a = addr & ~(sc_lsize - 1); end = (addr + size) & ~(sc_lsize - 1); while (1) { - flush_scache_line(a); /* Hit_Writeback_Inv_SD */ + invalidate_scache_line(a); /* Hit_Writeback_Inv_SD */ if (a == end) break; a += sc_lsize; } --- include/asm-mips/mips32_cache.h Wed Jul 3 08:30:08 2002 +++ ../../linux-2.4.18/sw/linux-2.4.18/include/asm-mips/mips32_cache.h Mon Jun 24 13:17:36 2002 @@ -37,41 +37,65 @@ static inline void flush_icache_line_indexed(unsigned long addr) { - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (addr), - "i" (Index_Invalidate_I)); + unsigned long waystep = icache_size/mips_cpu.icache.ways; + unsigned int way; + + for (way = 0; way < mips_cpu.icache.ways; way++) + { + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Index_Invalidate_I)); + + addr += waystep; + } } static inline void flush_dcache_line_indexed(unsigned long addr) { - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (addr), - "i" (Index_Writeback_Inv_D)); + unsigned long waystep = dcache_size/mips_cpu.dcache.ways; + unsigned int way; + + for (way = 0; way < mips_cpu.dcache.ways; way++) + { + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Index_Writeback_Inv_D)); + + addr += waystep; + } } static inline void flush_scache_line_indexed(unsigned long addr) { - __asm__ __volatile__( - ".set noreorder\n\t" - ".set mips3\n\t" - "cache %1, (%0)\n\t" - ".set mips0\n\t" - ".set reorder" - : - : "r" (addr), - "i" (Index_Writeback_Inv_SD)); + unsigned long waystep = scache_size/mips_cpu.scache.ways; + unsigned int way; + + for (way = 0; way < mips_cpu.scache.ways; way++) + { + __asm__ __volatile__( + ".set noreorder\n\t" + ".set mips3\n\t" + "cache %1, (%0)\n\t" + ".set mips0\n\t" + ".set reorder" + : + : "r" (addr), + "i" (Index_Writeback_Inv_SD)); + + addr += waystep; + } } static inline void flush_icache_line(unsigned long addr) @@ -210,12 +234,17 @@ static inline void blast_dcache_page_indexed(unsigned long page) { - unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - - while(start < end) { - cache_unroll(start,Index_Writeback_Inv_D); - start += dc_lsize; + unsigned long start; + unsigned long end = (page + PAGE_SIZE); + unsigned long waystep = dcache_size/mips_cpu.dcache.ways; + unsigned int way; + + for (way = 0; way < mips_cpu.dcache.ways; way++) { + start = page + way*waystep; + while(start < end) { + cache_unroll(start,Index_Writeback_Inv_D); + start += dc_lsize; + } } } @@ -243,12 +272,17 @@ static inline void blast_icache_page_indexed(unsigned long page) { - unsigned long start = page; - unsigned long end = (start + PAGE_SIZE); - - while(start < end) { - cache_unroll(start,Index_Invalidate_I); - start += ic_lsize; + unsigned long start; + unsigned long end = (page + PAGE_SIZE); + unsigned long waystep = icache_size/mips_cpu.icache.ways; + unsigned int way; + + for (way = 0; way < mips_cpu.icache.ways; way++) { + start = page + way*waystep; + while(start < end) { + cache_unroll(start,Index_Invalidate_I); + start += ic_lsize; + } } } @@ -276,12 +310,17 @@ static inline void blast_scache_page_indexed(unsigned long page) { - unsigned long start = page; - unsigned long end = page + PAGE_SIZE; - - while(start < end) { - cache_unroll(start,Index_Writeback_Inv_SD); - start += sc_lsize; + unsigned long start; + unsigned long end = (page + PAGE_SIZE); + unsigned long waystep = scache_size/mips_cpu.scache.ways; + unsigned int way; + + for (way = 0; way < mips_cpu.scache.ways; way++) { + start = page + way*waystep; + while(start < end) { + cache_unroll(start,Index_Writeback_Inv_SD); + start += sc_lsize; + } } }