I have attached a patch, containing some fixes for some of the cache routines. Most of it is related to the MIPS32/MIPS64 specific routines, but it also contain a fix, which appear to be needed in all of the dma flushing routines. The problem is that we sometimes flush a cache line too much. Ralf, could you please take a look at it ? /Carsten -- _ _ ____ ___ Carsten Langgaard Mailto:carstenl@mips.com |\ /|||___)(___ MIPS Denmark Direct: +45 4486 5527 | \/ ||| ____) Lautrupvang 4B Switch: +45 4486 5555 TECHNOLOGIES 2750 Ballerup Fax...: +45 4486 5556 Denmark http://www.mips.com