From: Paul Menzel <pmenzel@molgen.mpg.de>
To: Ralf Baechle <ralf@linux-mips.org>,
Paul Burton <paul.burton@mips.com>,
James Hogan <jhogan@kernel.org>
Cc: linux-mips@vger.kernel.org
Subject: [PATCH] mips/cavium-octeon: Fix typo *must* in comment
Date: Thu, 17 Oct 2019 12:24:57 +0200 [thread overview]
Message-ID: <3a1eda2f-bc4b-0958-d609-6376663faa9a@molgen.mpg.de> (raw)
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Date: Mon, 2 Sep 2019 11:55:06 +0200
Fixes: 5b3b16880f ("MIPS: Add Cavium OCTEON processor support files to arch/mips/cavium-octeon.")
Signed-off-by: Paul Menzel <pmenzel@molgen.mpg.de>
---
arch/mips/cavium-octeon/setup.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/mips/cavium-octeon/setup.c b/arch/mips/cavium-octeon/setup.c
index 95034bf5ca83..1f742c32a883 100644
--- a/arch/mips/cavium-octeon/setup.c
+++ b/arch/mips/cavium-octeon/setup.c
@@ -844,7 +844,7 @@ void __init prom_init(void)
* BIST should always be enabled when doing a soft reset. L2
* Cache locking for instance is not cleared unless BIST is
* enabled. Unfortunately due to a chip errata G-200 for
- * Cn38XX and CN31XX, BIST msut be disabled on these parts.
+ * Cn38XX and CN31XX, BIST must be disabled on these parts.
*/
if (OCTEON_IS_MODEL(OCTEON_CN38XX_PASS2) ||
OCTEON_IS_MODEL(OCTEON_CN31XX))
--
2.22.0
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next reply other threads:[~2019-10-17 10:25 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-17 10:24 Paul Menzel [this message]
2019-11-01 23:28 ` [PATCH] mips/cavium-octeon: Fix typo *must* in comment Paul Burton
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