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Subject: Re: [PATCH v4 1/8] MIPS: Loongson: Merge RPID macro for
 Loongson-1A/1B/1C
To:     Binbin Zhou <zhoubb@lemote.com>, Ralf Baechle <ralf@linux-mips.org>
References: <1486452550-10721-1-git-send-email-zhoubb@lemote.com>
 <1486452550-10721-2-git-send-email-zhoubb@lemote.com>
Cc:     John Crispin <john@phrozen.org>,
        "Steven J . Hill" <Steven.Hill@imgtec.com>,
        linux-mips@linux-mips.org, Fuxin Zhang <zhangfx@lemote.com>,
        Zhangjin Wu <wuzhangjin@gmail.com>,
        Kelvin Cheung <keguang.zhang@gmail.com>,
        Yang Ling <gnaygnil@gmail.com>, HuaCai Chen <chenhc@lemote.com>
From:   Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Message-ID: <3d751d79-d60c-e3f1-ebb9-1538820ae8ed@cogentembedded.com>
Date:   Tue, 7 Feb 2017 12:26:20 +0300
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Hello!

On 2/7/2017 10:29 AM, Binbin Zhou wrote:

> The Loongson-1 series CPUs(1A/1B/1C) share the same RPID macro.

    Maybe PRID?

> Signed-off-by: Binbin Zhou <zhoubb@lemote.com>
> Signed-off-by: HuaCai Chen <chenhc@lemote.com>
[...]

MBR, Sergei