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Tue, 1 Apr 2025 05:31:38 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-mips@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: Tf2d86106c131fe8c Date: Tue, 01 Apr 2025 10:31:17 +0100 From: "Jiaxun Yang" To: "Maciej W. Rozycki" , "Marco Crivellari" Cc: "linux-mips@vger.kernel.org" , linux-kernel@vger.kernel.org, "Thomas Bogendoerfer" , "Frederic Weisbecker" , "Anna-Maria Behnsen" , "Thomas Gleixner" , "Peter Zijlstra" , "Huacai Chen" Message-Id: <3f7f6ced-98e8-4101-aa83-3692e14222ca@app.fastmail.com> In-Reply-To: References: <20250315194002.13778-1-marco.crivellari@suse.com> <20250315194002.13778-2-marco.crivellari@suse.com> Subject: Re: [PATCH v6 1/1] MIPS: Fix idle VS timer enqueue Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82025=E5=B9=B43=E6=9C=8831=E6=97=A5=E6=98=9F=E6=9C=9F=E5=91=A8=E4= =B8=80 =E4=B8=8B=E5=8D=889:09=EF=BC=8CMaciej W. Rozycki=E5=86=99=E9=81=93= =EF=BC=9A [...] > > FAOD I have one MIPS32r2 system wired for testing, but that might not= be=20 > the most interesting configuration to verify as it'll now just use EI/= EHB=20 > to enable interrupts ahead of WAIT. I could try an R1 kernel instead,= but=20 > I'm not sure if it can be made to work owing to the differences in the= FPU=20 > between R1 and R2 for the MIPS32 ISA. I used to have a MIPS64 (R1) sy= stem=20 > there, but the CPU daughtercard sadly stopped working 3 years ago and = I=20 > wasn't able to repair it, owing to the lack of available spare parts (= it's=20 > most likely a dead CPU). I can test on legacy (R1 version) 4Kc RTL simulator if you wish. Is ther= e any thing specific you want to test? I think I can try interrupt flood and s= ee if there is any deadlock. The simulation is painfully slow, so I'd wish to minimize test vector. Thanks --=20 - Jiaxun