From: "Steven J. Hill" <sjhill@realitydiluted.com>
To: Ralf Baechle <ralf@linux-mips.org>
Cc: "Kevin D. Kissell" <kevink@mips.com>,
Brian Murphy <brian@murphy.dk>,
linux-mips@linux-mips.org
Subject: Re: BUG in pcnet32.c?
Date: Mon, 29 Mar 2004 21:30:38 -0500 [thread overview]
Message-ID: <4068DBCE.8000702@realitydiluted.com> (raw)
In-Reply-To: <20040330012403.GB4068@linux-mips.org>
Ralf Baechle wrote:
>
> The change goes beyond just cache managment; the API also abstracts away
> I/O MMUs which so far are quite rare on MIPS systems - but I really hope
> they're going to establish themselves asap.
>
> The Documentation/DMA-API.txt also documents how properly deal with cache
> alignment when using this API.
>
> Steven, maybe that we should add another assertion to make sure we don't
> run into trouble with missaligned cachelines?
>
Okay. I will have a look at tomorrow morning.
-Steve
next prev parent reply other threads:[~2004-03-30 2:30 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2004-03-29 20:01 BUG in pcnet32.c? Brian Murphy
2004-03-29 20:25 ` Steven J. Hill
2004-03-29 20:55 ` Kevin D. Kissell
2004-03-29 20:55 ` Kevin D. Kissell
2004-03-29 20:58 ` Steven J. Hill
2004-03-30 1:24 ` Ralf Baechle
2004-03-30 2:30 ` Steven J. Hill [this message]
2004-03-31 20:48 ` Brian Murphy
2004-04-01 8:31 ` Geert Uytterhoeven
2004-04-01 17:31 ` Ralf Baechle
2004-04-02 8:27 ` Brian Murphy
2004-04-02 8:39 ` Ralf Baechle
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