Re: [Patch] Fix lookup_dcookie for MIPS o32

[David Daney <ddaney@avtrex.com>]

Ralf Baechle wrote:
> On Tue, Oct 18, 2005 at 09:04:49AM -0700, David Daney wrote:
> 
> 
>>The CPU has performance counters, but they cannot trigger interrupts, so 
>>I am just using it in 'timer' mode right now.  I am wondering what would 
>>happen if I added all counter samples at each clock tick.  That is 
>>something I might try when I have a little free time.
> 
> 
> Now that's truly a strange processor - what CPU are you using?
> 

ATI Xilleon X226-A12.  According to my data sheet, there are ten 
counters, but you can only use six at a time.  They are external to the 
4KEc core, and the only operations you can do to them are enable/disable 
counting, reset to zero and read the current values.

The counters count:
I cache hit/miss
D cache hit/miss
TLB hit/miss
JTLB hit/miss
Write merging/not merging

Perhaps I should not worry about them.  Probably hooking up one of the 
high resolution timers would yield more useful profiling information.


> 
>>I had one other problem with my cross built bash where the signal 
>>numbering of the build host was being used instead of the numbering for 
>>the target.  Once I fixed bash and the lookup_dcookie system call, it 
>>seems to work flawlessly.
> 
> 
> That bug is getting a classic.  I've fixed it in ash also - ages ago ...
> 
> I usually try to escape from the horrors of crosscompiling by using a
> decent GHz MIPS system.
> 

Yeah, In a perfect world I would have such a beast.

David Daney