This is Peter Horton's IDE patch for the Cobalt. From the notes in 
Peter's file.

PIO "in" transfers can cause D-cache lines to be allocated
 to the data being read. If the target is the page cache then
 the kernel can create a user space mapping of the same page
 without flushing it from the D-cache. This has large potential
 to create cache aliases. The Cobalts seem to trigger this
 problem easily.


-- 
----
Jim Gifford
maillist@jg555.com