From: Sergei Shtylyov <sshtylyov@ru.mvista.com>
To: linux-mips <linux-mips@linux-mips.org>
Cc: Clem Taylor <clem.taylor@gmail.com>,
Jordan Crouse <jordan.crouse@amd.com>,
Manish Lachwani <mlachwani@mvista.com>
Subject: [PATCH] FIx mprotect() syscall for MIPS32 w/36-bit physical address support
Date: Sat, 08 Apr 2006 03:09:52 +0400 [thread overview]
Message-ID: <4436F140.3030007@ru.mvista.com> (raw)
In-Reply-To: <20060202165436.GB17352@linux-mips.org>
[-- Attachment #1: Type: text/plain, Size: 248 bytes --]
Hello.
Fix mprotect() syscall for MIPS32 CPUs with 36-bit physical address
support: pte_modify() macro didn't clear the hardware page protection bits
before modifying...
WBR, Sergei
Signed-off-by: Sergei Shtylyov <sshtylyov@ru.mvista.com>
[-- Attachment #2: MIPS32-36bit-phys-addr-mprotect-fix.patch --]
[-- Type: text/plain, Size: 593 bytes --]
diff --git a/include/asm-mips/pgtable.h b/include/asm-mips/pgtable.h
index 702a28f..80b3605 100644
--- a/include/asm-mips/pgtable.h
+++ b/include/asm-mips/pgtable.h
@@ -335,8 +335,9 @@ static inline pgprot_t pgprot_noncached(
#if defined(CONFIG_64BIT_PHYS_ADDR) && defined(CONFIG_CPU_MIPS32_R1)
static inline pte_t pte_modify(pte_t pte, pgprot_t newprot)
{
- pte.pte_low &= _PAGE_CHG_MASK;
- pte.pte_low |= pgprot_val(newprot);
+ pte.pte_low &= _PAGE_CHG_MASK;
+ pte.pte_high &= ~0x3f;
+ pte.pte_low |= pgprot_val(newprot);
pte.pte_high |= pgprot_val(newprot) & 0x3f;
return pte;
}
prev parent reply other threads:[~2006-04-07 23:00 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2005-12-07 21:51 can read/write to mprotect(PROT_NONE) region with 2.6.14 on au1550 Clem Taylor
2006-02-02 16:54 ` Ralf Baechle
2006-04-07 23:09 ` Sergei Shtylyov [this message]
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