Re: [PATCH] [MIPS] Fixed PCI resource fixup

[Peter Horton <phorton@bitbox.co.uk>]

Ralf Baechle wrote:
> On Fri, Jan 12, 2007 at 02:49:05PM +0000, Alan wrote:
> 
>>>> The GT-64111 passes the CPU addresses straight onto the PCI bus and does 
>>>> not remove the offset of the Galileo's PCI window in CPU space. This 
>>>> means the only PCI I/O addresses that can be supported are 0x1000.0000 
>>>> to 0x11ff.ffff, hence the negative 'io_offset'.
>> Does this mean it can't hit PCI I/O space legacy addresses (0x1F0 etc) ?
>>
>> If so can you set CONFIG_NO_ATA_LEGACY in your platform configuration
> 
> In the meantime I checked this against the Galileo documentation.  Which
> says just like Yoichi and Peter that the GT-64111 is passing local
> addresses in the configured PCI memory or I/O windows straight through to
> the PCI bus.  Reconfiguring the PCI I/O window to start at physical address
> zero is not really an option because the CPU has it's exception vectors
> there.
> 
> There is one inconsistency in the whole story still.  Cobalts use a PC-style
> legacy RTC chip at I/O port 0x70 and that seems to work just fine.  I suspect
> the the VIA Apollo SuperIO chip makes this work by just dropping some of the
> high I/O port address bits ...
> 

I've just checked on the Qube2 here and the RTC can be found at 
0x1000.0070, 0x1001.0070 etc so the VIA bridge is only decoding the low 
16 address lines for I/O space. Handy really otherwise it wouldn't work 
with the GT-64111 :-)

P.