Here is a patch (for 2.6.21 git as of 2007-04-27) with complete support for alchemy au1550 psc spi controller. It supports dma transfers using alchemy descriptor based dma controller for 4 to 8 bits per spi word transfers. For 9 to 24 bits per spi word transfers, pio irq based mode is used to avoid setup of dma channels from scratch on each number of bits per word change. Tested with au1550, may also work on other mips alchemy cpus, like au1200/au1210/au1250. Used extensively with SD card connected via SPI, handles 8.1MHz spi clock transfers using dma without any problem (the highest spi clock freq possible to get internally with au1550 running on 324MHz). The driver supports sharing of spi bus by multiple devices, all features of alchemy spi controller are supported (all spi modes, msb/lsb first, bits per word in 4 to 24 range). As the spi clock of the controller depends on main input clock that shall be configured externally, platform data structure for au1550 spi controller driver contains mainclk_hz attribute to define the input clock hz - from this value, dividers of the controller for spi clock are set up for required frequency. Jan Signed-off-by: Jan Nikitenko drivers/spi/Kconfig | 11 drivers/spi/Makefile | 1 drivers/spi/au1550_spi.c | 959 ++++++++++++++++++++++++++++++ include/asm-mips/mach-au1x00/au1550_spi.h | 16 4 files changed, 987 insertions(+)