Re: about cs5536 interrupt ack

[Songmao Tian <tiansm@lemote.com>]

Songmao Tian wrote:
> Hi,
>    I am trying to use a mips cpu the cs5536. I have some problem with 
> the 8259 of cs5536.  The  databook said,

cs5536 is a south bridge, cpu, of couse, is loongson:)

>
> "Control Logic
> The INT output goes directly to the CPU interrupt input.
> When an INT signal is activated, the CPU responds with an
> Interrupt Acknowledge access that is translated to two
> pulses on the INTA input of the PIC. At the first INTA pulse,
> the highest priority IRR bit is loaded into the corresponding
> ISR bit, and that IRR bit is reset. The second INTA pulse
> instructs the PIC to present the 8-bit vector of the interrupt
> handler onto the data bus."
>
> Is it the responsibility of north bridge to reponse to intr with a PCI 
> Interrupt Ack cycle?
> it's a problem that my northbridge didn't implement that! Fortunately 
> we use a fpga as a northbridge.
>
> it seem it's no way to fix this by software, for OCW3 didn't implemnt 
> Poll command:(
>
> so I guess the the process is:
> 1) 8259 receive a int, a bit irr got set.
> 2) 8259 assert intr.
> 3) northbrige generate a int ack cycle.
> 4) cs5536 translate the ack into two INTA pulse, and the reponse 
> northbridge with a interrupt vector.
> 5) then my program can get the vector from northbridge?
>
> Is that right?
>
> Without int ack, generic linux-mips 8259 code can't work.
>
> Greetings,
> Tian
>
>
>
>
>
>