From: Aurelien Jarno <aurelien@aurel32.net>
To: Alan Cox <alan@lxorguk.ukuu.org.uk>
Cc: qemu-devel@nongnu.org, linux-mips@linux-mips.org
Subject: Re: [Qemu-devel] QEMU/MIPS & dyntick kernel
Date: Tue, 02 Oct 2007 22:57:24 +0200 [thread overview]
Message-ID: <4702B0B4.6080909@aurel32.net> (raw)
In-Reply-To: <20071002214826.7ee2fae8@the-village.bc.nu>
Alan Cox a écrit :
>> Well on real hardware, the instruction rate and the timer are linked:
>> the timer run at half the speed of the CPU. As the corresponding
>> assembly code is very small, only uses registers and is run in kernel
>> mode, you know for sure that 48 cycles is more than enough.
>
> What happens on NMI or if you take an ECC exception and scrubbing stall
> off the memory controller while loading part of that cache line of code
> into memory ?
>
The code returns -ETIME, and the function is run again with the minimum
delay.
So as long as you don't have an exception every time, the code works.
--
.''`. Aurelien Jarno | GPG: 1024D/F1BCDB73
: :' : Debian developer | Electrical Engineer
`. `' aurel32@debian.org | aurelien@aurel32.net
`- people.debian.org/~aurel32 | www.aurel32.net
next prev parent reply other threads:[~2007-10-02 20:57 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2007-10-02 20:06 QEMU/MIPS & dyntick kernel Aurelien Jarno
2007-10-02 20:27 ` [Qemu-devel] " Avi Kivity
2007-10-02 20:37 ` Aurelien Jarno
2007-10-02 20:48 ` Alan Cox
2007-10-02 20:57 ` Aurelien Jarno [this message]
2007-10-02 22:35 ` Ralf Baechle
2007-10-15 15:05 ` Thiemo Seufer
2007-10-15 15:58 ` Ralf Baechle
2007-10-15 16:20 ` Thiemo Seufer
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