From: Sven Eckelmann <sven@narfation.org>
To: linux-mips@linux-mips.org, Ralf Baechle <ralf@linux-mips.org>,
Paul Burton <paul.burton@imgtec.com>
Cc: Paul Burton <paul.burton@imgtec.com>,
James Hogan <james.hogan@imgtec.com>,
Joshua Kinard <kumba@gentoo.org>,
Paul Gortmaker <paul.gortmaker@windriver.com>,
linux-kernel@vger.kernel.org,
"Maciej W. Rozycki" <macro@codesourcery.com>,
Markos Chandras <markos.chandras@imgtec.com>,
"Kirill A. Shutemov" <kirill.shutemov@linux.intel.com>,
David Bauer <mail@david-bauer.net>
Subject: Re: [PATCH 1/2] MIPS: Add barriers between dcache & icache flushes
Date: Mon, 06 Mar 2023 11:28:15 +0100 [thread overview]
Message-ID: <4818332.31r3eYUQgx@ripper> (raw)
In-Reply-To: <1456164585-26910-1-git-send-email-paul.burton@imgtec.com>
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On Monday, 22 February 2016 19:09:44 CET Paul Burton wrote:
> Index-based cache operations may be arbitrarily reordered by out of
> order CPUs. Thus code which writes back the dcache & then invalidates
> the icache using indexed cache ops must include a barrier between
> operating on the 2 caches in order to prevent the scenario in which:
>
> - icache invalidation occurs.
>
> - icache fetch occurs, due to speculation.
>
> - dcache writeback occurs.
>
> If the above were allowed to happen then the icache would contain stale
> data. Forcing the dcache writeback to complete before the icache
> invalidation avoids this.
>
> Signed-off-by: Paul Burton <paul.burton@imgtec.com>
> Cc: James Hogan <james.hogan@imgtec.com>
> ---
What happened to this patch? Because it seems like it is required for some
74kc devices to get them booting (instead of being stuck in an endless
tlbmiss_handler_setup_pgd loop):
* https://github.com/freifunk-gluon/gluon/issues/2784
* https://github.com/openwrt/openwrt/commit/ea6fb9c16dfb9763ea681803db65644b68bae873
* https://github.com/freifunk-gluon/gluon/pull/2810
Kind regards,
Sven
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prev parent reply other threads:[~2023-03-06 10:45 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-02-22 18:09 [PATCH 1/2] MIPS: Add barriers between dcache & icache flushes Paul Burton
2016-02-22 18:09 ` Paul Burton
2016-02-22 18:09 ` [PATCH 2/2] MIPS: Flush highmem pages from dcache in __flush_icache_page Paul Burton
2016-02-22 18:09 ` Paul Burton
2016-02-24 8:02 ` Lars Persson
2016-02-24 8:02 ` Lars Persson
2016-02-22 23:39 ` [PATCH 1/2] MIPS: Add barriers between dcache & icache flushes Joshua Kinard
2016-03-01 2:23 ` Paul Burton
2016-03-01 2:23 ` Paul Burton
2016-02-23 0:02 ` Florian Fainelli
2016-03-01 2:27 ` Paul Burton
2016-03-01 2:27 ` Paul Burton
2023-03-06 10:28 ` Sven Eckelmann [this message]
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